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K4M511633E-F1H Dataheets PDF



Part Number K4M511633E-F1H
Manufacturers Samsung
Logo Samsung
Description 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
Datasheet K4M511633E-F1H DatasheetK4M511633E-F1H Datasheet (PDF)

K4M511633E - Y(P)C/L/F 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 3.0V or 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Sup.

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K4M511633E - Y(P)C/L/F 8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 3.0V or 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • 64ms refresh period (8K cycle). • Commercial Temperature Operation (-25°C ~ 70°C). • 1 /CS Support. • 2chips DDP 54Balls FBGA with 0.8mm ball pitch ( -YXXX : Leaded, -PXXX : Lead Free). Mobile-SDRAM GENERAL DESCRIPTION The K4M511633E is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4M511633E-Y(P)C/L/F75 K4M511633E-Y(P)C/L/F1H K4M511633E-Y(P)C/L/F1L Max Freq. 133MHz(CL=3) 105MHz(CL=2) 105MHz(CL=3)*1 LVCMOS 54 FBGA Leaded (Lead Free) Interface Package - Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C) Notes : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other products or other applications under paragrangh such as mobile, telecom or non-computer application(which include by way of example laptop or notebook computers, cell phones, televisions or visual monitors). Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." 3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. February 2004 K4M511633E - Y(P)C/L/F FUNCTIONAL BLOCK DIAGRAM Mobile-SDRAM I/O Control LWE Data Input Register Bank Select LDQM 8M x.


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