M54HC238

M54HC238 M74HC238 3 TO 8 LINE DECODER . . . . . . . . HIGH SPEED tPD = 14 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS238 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC238F1R M74HC238M1R M74HC238B1R M74HC238C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC238 is a high speed CMOS 3 to 8 line 2 decoder fabricated in silicon gate C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. If the device is enabled, 3 binary select inputs (A, B and C) determine which one of outputs will go high. Enable input G1 is held ”Low” or either G2A or G2B is held ”High” decoding function is inhibited and all the 8 outputs go low. Three enable inputs are provided to ease cascade connection and application of this address decoder in memory systems. All inputs are equipped with protection circuits against static discharge and transient excess voltage. NC = No Internal Connection October 1993 1/10 M54/M74HC238 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 2, 3 4, 5 6 15, 14, 13, 12, 11, 10, 9, 7 8 16 SYMBOL A, B, C G2A G2B G1 Y0 to Y7 NAME AND FUNCTI...