TDA1305T

INTEGRATED CIRCUITS DATA SHEET TDA1305T Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2) Preliminary specification Supersedes data of September 1994 File under Integrated Circuits, IC01 1995 Dec 08 Philips Semiconductors Preliminary specification Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2) FEATURES Easy application 16fs Finite-duration Impulse-Response (FIR) filter incorporated Selectable system clock (fsys) 256fs or 384fs I2S-bus serial input format (at fsys = 256fs) or LSB fixed 16, 18 or 20 bits serial input mode (at fsys = 384fs) Slave-mode clock system Cascaded 4-stage digital filter incorporating 2-stage FIR filter, linear interpolator and sample-and-hold Smoothed transitions before and after muting (soft mute) Digital de-emphasis filter for three sampling rates of 32 kHz, 44.1 kHz and 48 kHz 12 dB attenuation via the attenuation input control Double speed mode 2nd order noise shaper 96 (fsys = 384fs) or 128 (fsys = 256fs) times oversampling in normal speed mode 48 (fsys = 384fs) or 64 (fsys = 256fs) times oversampling in double speed mode Bitstream continuous calibration concept Small outline SO28 package Voltage output 1.5 V (RMS) at line drive level Low total harmonic distortion No zero crossing distortion Inherently monotonic No analog post filtering required Superior signal-to-noise ratio Wide dynamic range (18-bit) Single rail supply (3....