Document
TC74VHCT573AF/AFK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHCT573AF, TC74VHCT573AFK
Octal D-Type Latch with 3-State Output
The TC74VHCT573A is an advanced high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ).
When the OE input is high, the eight outputs are in a high impedance state.
The input voltage are compatible with TTL output voltage. This device may be used as a level converter for interfacing 3.3 V to 5 V system. Input protection and output circuit ensure that 0 to 5.5 V can be applied to the input and output (Note) pins without regard to the supply voltage. These structure prevents device destruction due to mismatched supply and input/output voltages such as battery back up, hot board insertion, etc.
Note: Output in off-state
TC74VHCT573AF TC74VHCT573AFK
Features
High speed: tpd 7.7 ns (typ.) at VCC 5 V Low power dissipation: ICC 4 A (max) at Ta 25°C
Weight SOP20-P-300-1.27A: VSSOP20-P-0030-0.50:
Compatible with TTL inputs:
VIL 0.8 V (max) VIH 2.0 V (min)
Power down protection is provided on all inputs and outputs.
Balanced propagation delays: tpLH tpHL
Low noise: VOLP 1.5 V (max)
Pin and function compatible with the 74 series (74AC/HC/F/ALS/LS etc.) 573 type.
0.22 g (typ.) 0.03 g (typ.)
© 2019
1
Toshiba Electronic Devices & Storage Corporation
Start of commercial production
1995-12
2019-01-31
Pin Assignment
TC74VHCT573AF/AFK
IEC Logic Symbol
1 D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 GND 10
(top view)
20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE
(1) EN LE (11) C1
D0 (2) 1D D1 (3) D2 (4) D3 (5) D4 (6) D5 (7) D6 (8) D7 (9)
(19) Q0 (18) Q1 (17) Q2 (16) Q3 (15) Q4 (14) Q5 (13) Q6 (12) Q7
Truth Table
Inputs
OE LE
D
H
X
X
L
L
X
L
H
L
L
H
H
Output
Z Qn L H
X: Don’t care Z: High impedance Qn: Q outputs are latched at the time when the LE input is taken to a low logic level.
System Diagram
D0 2
D
D1 3
D
D2 4
D
D3 5
D
D4 6
D
D5 7
D
D6 8
D
D7 9
D
11 LE
L
L
L
L
L
L
L
L
1
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
6Q6
Q7
© 2019
2
Toshiba Electronic Devices & Storage Corporation
2019-01-31
Absolute Maximum Ratings (Note 1)
TC74VHCT573AF/AFK
Characteristics
Symbol
Rating
Unit
Supply voltage range DC input voltage
DC output voltage
Input diode current Output diode current DC output current DC VCC/ground current Power dissipation Storage temperature
VCC VIN
VOUT
IIK IOK IOUT ICC PD Tstg
−0.5 to 7.0
V
−0.5 to 7.0
V
−0.5 to 7.0 (Note 2) V
−0.5 to VCC + 0.5 (Note 3)
−20
mA
±20
(Note 4) mA
±25
mA
±75
mA
180
mW
−65 to 150
°C
Note 1:
Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in I.