DatasheetsPDF.com

IDT74FCT377AT

Integrated Device Tech

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE

FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE Integrated Device Technology, Inc. IDT54/74FCT377T/AT/CT/DT FEATURES: • ...


Integrated Device Tech

IDT74FCT377AT

File Download Download IDT74FCT377AT Datasheet


Description
FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE Integrated Device Technology, Inc. IDT54/74FCT377T/AT/CT/DT FEATURES: Std., A, C and D speed grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) High drive outputs (-15mA IOH, 48mA IOL) Power off disable outputs permit “live insertion” Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, QSOP, CERPACK and LCC packages DESCRIPTION: The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT377T/AT/CT/DT have eight edge-triggered, D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. FUNCTIONAL BLOCK DIAGRAM D0 CE D1 D2 D3 D4 D5 D6 D7 D Q CP CP O0 D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP O1 O2 O3 O4 O5 O6 O7 2630 drw 01 The IDT logo is a registered trademark of Integ...




Similar Datasheet




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)