FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARYANDINDUSTRIALTEMPERATURERANGES
FAST CMOS O...
Description
IDT54/74FCT273T/AT/CT FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARYANDINDUSTRIALTEMPERATURERANGES
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
IDT54/74FCT273T/AT/CT
FEATURES:
Std., A, and C grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility:
– VOH = 3.3V (typ.) – VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: – Industrial: SOIC, SSOP, QSOP – Military: CERDIP, LCC
DESCRIPTION:
The FCT273T is an octal D flip-flop built using an advanced dual metal CMOS technology. The FCT273T has eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by a low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7 CP
DQ
DQ
DQ
DQ
DQ
...
Similar Datasheet