Document
FAST CMOS OCTAL D REGISTERS (3-STATE)
Integrated Device Technology, Inc.
IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT IDT54/74FCT534T/AT/CT IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT
FEATURES:
• Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT374T/FCT534T/FCT574T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) • Features for FCT2374T/FCT2574T: – Std., A, and C speed grades – Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) – Reduced system switching noise
DESCRIPTION
The FCT374T/FCT2374T, FCT534T and FCT574T/ FCT2574T are 8-bit registers built using an advanced dual metal CMOS technology. These registers consist of eight Dtype flip-flops with a buffered common clock and buffered 3state output control. When the output enable (OE) input is LOW, the eight outputs are enabled. When the OE input is HIGH, the outputs are in the high-impedance state. Input data meeting the set-up and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-toHIGH transition of the clock input. The FCT2374T and FCT2574T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. FCT2xxxT parts are plug-in replacements for FCTxxxT parts.
FUNCTIONAL BLOCK DIAGRAM FCT374/FCT2374T AND FCT574/FCT2574T
D0 CP CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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FUNCTIONAL BLOCK DIAGRAM FCT534T
D0 CP CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q CP D Q D1 D2 D3 D4 D5 D6 D7
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-4214/5
6.13
1
IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT374T
1 2 3 4 5 6 7 8 9 10 20 19 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
3 D1 Q1 Q2 D2 D3 4 5 6 7 8
Q0 OE
2 1
D0
INDEX
VCC Q7
20 19 18 17 16 15
D7 D6 Q6 Q5 D5
L20-2
14 9 10 11 12 13
GND
CP
Q3
Q4
D4
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DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
IDT54/74FCT574T
VCC OE
1 INDEX
D1
D0
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
1 2 3 4 5 6 7 8 9 10
20 19 P20-1 18 D20-1 17 SO20-2 16 SO20-7 15 SO20-8 14 & E20-1 13 12 11
VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP
3 2 D2 D3 D4 D5 D6 4 5 6 7 8
20 19 18 17 16 15 14
Q0
Q1 Q2 Q3 Q4 Q5
L20-2
9 10 11 12 13
D7
GND
CP
Q7 Q6
DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW
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LCC TOP VIEW
IDT54/74FCT534T
Q0 OE
1
OE Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
1 2 3 4 5 6 7 8 9 10 P20-1 D20-1 SO20-2 SO20-8 & E20-1
20 19 18 17 16 15 14 13 12 11
VCC Q7 D7 D6 Q6 Q5 D5 D4
GND
3 2 D1 Q1 Q2 D2 D3 4 5 6 7 8 L20-2 20 19 18 17 16 15 14 9 10 11 12 13 D7 D6 Q6 Q5 D5
D0
INDEX
Q4 CP
CP Q4 D4
Q3
VCC Q7
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DIP/SOIC/QSOP/CERPACK TOP VIEW
LCC TOP VIEW
6.13
2
IDT54/74FCT374T/AT/CT/DT - 2374T/AT/CT, IDT54/74FCT534T/AT/CT, IDT54/74FCT574T/AT/CT/DT - 2574T/AT/CT FAST CMOS OCTAL D REGISTERS (3-STATE) MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION
Pin Names DN CP QN Description D flip-flop data inputs Clock Pulse for the register. Enters data on LOW-to-HIGH transition. 3-state outputs, (true) 3-state outputs, (inverted) Active LOW 3-state Output Enable input
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QN OE
FUNCTION TABLE(1)
534 Inputs Function
HI-Z LOAD REGISTER
Outputs DN X X L H L H
Internal QN NC NC L H L H
374/574 Outputs Internal QN Z Z L H Z Z
OE
H H L L H H
CP L H
QN
Z Z H L Z Z
QN
NC NC H L H L
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↑ ↑ ↑ ↑
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance NC = No Change ↑ = LOW-to-HIGH transition
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current –60 to +120 Military –0.5 to +7.0 Unit V
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit 10 pF 12
pF
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–0.5 to VCC +0.5 –55 to +125 –65 to +135 –65 .