IDT72V255LA

3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18 FEATURES: IDT72V255LA IDT72V265LA Choose among the following memory organizations: IDT72V255LA 8,192 x 18 IDT72V265LA 16,384 x 18 Pin-compatible with the IDT72V275/72V285 and IDT72V295/ 72V2105 SuperSync FIFOs Functionally compatible with the 5 Volt IDT72255/72265 family 10ns read/write cycle time (6.5ns access time) Fixed, low first word data latency time 5V input tolerant Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Retransmit operation with fixed, low first word data latency time Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of two preselected offsets Program partial flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance state Easily expandable in depth and width Independent Read and Write clocks (permit reading and writing simultaneously) Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64pin Slim Thin Quad Flat Pack (STQFP) High-performance submicron CMOS technology Industrial temperature range (–40°C to +85°C) is available DESCRIPTION: The IDT72V255LA/72V265LA are functionally compatible versions of the IDT72255/72265 designed to run off a ...