IC43R16800

IC43R16800 Document Title 2M x 16 Bit x 4 Banks (128-MBIT) DDR SDRAM Revision History Revision No 0A 0B History Initial Draft Mass production Draft Date January 20,2004 November 10,2004 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DDR002-0B 11/10/2004 1 IC43R16800 2M Words x 16 Bits x 4 Banks (128-MBIT) DDR SYNCHRONOUS DYNAMIC RAM 5 Clock Cycle Time (tCK2) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK3) System Frequency (fCK max) DDR400 7.5ns 6ns 5ns 200MHz 6 DDR333 7.5ns 6ns 166MHz 7 DDR266 7.5ns 7ns 143MHz ■ High speed data transfer rates with system frequency up to 200 MHz ■ Data Mask for Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 2, 2.5, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type ■ Automatic and Controlled Precharge Command ■ Power Down Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 4096 cycles/64 ms ■ Available in 66-pin 400 mil TSOP ■ SSTL-2 Compatible I/Os ■ Double Data Rate (DDR) ■ Bidirectional Data Strobe (DQS) for input and output data, active on both edges ■ On-Chip DLL aligns DQ and DQs transitions with CK transitions ■ Differential clock inputs CK and CK Features The ...