W183-5

W183 Full Feature Peak Reducing EMI Solution Features Cypress PREMIS™ family offering Generates an EMI optimized clocking signal at the output Selectable output frequency range Single 1.25%, 3.75% down or center spread output Integrated loop filter components Operates with a 3.3 or 5V supply Low power CMOS design Available in 14-pin SOIC (Small Outline Integrated Circuit) Table 1. Modulation Width Selection SS% 0 1 W183 Output Fin ≥ Fout ≥ Fin – 1.25% Fin ≥ Fout ≥ Fin – 3.75% W183-5 Output Fin + 0.625% ≥ Fin≥ – 0.625% Fin + 1.875% ≥ Fin≥ –1.875% Table 2. Frequency Range Selection FS2 0 0 1 1 FS1 0 1 0 1 Frequency Range 28 MHz ≤ FIN ≤ 38 MHz 38 MHz ≤ FIN ≤ 48 MHz 46 MHz ≤ FIN ≤ 60 MHz 58 MHz ≤ FIN ≤ 75 MHz Key Specifications Supply Voltages: ........................................... VDD = 3.3V±5% or VDD = 5V±10% Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz Crystal Reference Range:................. 28 MHz ≤ Fin ≤ 40 MHz Cycle to Cycle Jitter: ....................................... 300 ps (max.) Selectable Spread Percentage: ....................1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.) Simplified Block Diagram 3.3V or 5.0V Pin Configuration SOIC FS2 CLKIN or X1 NC or X2 GND GND SS% FS1 1 2 3 4 5 6 14 13 12 11 10 9 8 REFOUT OE# SSON# Reset VDD VDD CLKOUT W183/W183-5 X1 XTAL Input X2 40 MHz Max W183 Spread Spectr...