DatasheetsPDF.com

S2060B Dataheets PDF



Part Number S2060B
Manufacturers ETC
Logo ETC
Description GIGABIT ETHERNET TRANSCEIVER
Datasheet S2060B DatasheetS2060B Datasheet (PDF)

® DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION S2060 S2060 FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz (Gigabit Ethernet) line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit Ethernet standard Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference Receiver PLL provides clock and data recovery 10-bit parallel TTL compatible interface Low-jitter serial LVPECL.

  S2060B   S2060B



Document
® DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER GIGABIT ETHERNET TRANSCEIVER GENERAL DESCRIPTION S2060 S2060 FEATURES • • • • • • • • • • • • • Operating rate 1250 MHz (Gigabit Ethernet) line rates Half and full VCO output rates Functionally compliant IEEE 802.3z Gigabit Ethernet standard Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference Receiver PLL provides clock and data recovery 10-bit parallel TTL compatible interface Low-jitter serial LVPECL compatible interface Local loopback Single +3.3 V supply, 620 mW power dissipation 64 PQFP or TQFP package Continuous downstream clocking from receiver Drives 30 m of Twinax cable directly The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber optic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word. The chip provides parallel-to-serial and serial-to-parallel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a lowspeed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW. The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip. APPLICATIONS • • • • • Workstation Frame buffer Switched networks Data broadcast environments Proprietary extended backplanes Figure 1. System Block Diagram Gigabit Ethernet Controller Optical Tx S2060 Optical Rx Optical Rx S2060 Optical Tx Gigabit Ethernet Controller March 7, 2001 / Revision H 1 S2060 S2060 OVERVIEW The S2060 transmitter and receiver provide serialization and deserialization functions for block encoded data to implement a Gigabit Ethernet interface. The S2060 functional block diagram is depicted in Figure 2. The sequence of operations is as follows: Transmitter 1.10-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. Frame detection 4. 10-bit parallel output The 10-bit parallel data input to the S2060 should be from a DC-balanced encoding scheme, such as the 8B/10B transmission code, in which information to be transmitted is encoded 8 bits at a time into 10-bit trans- GIGABIT ETHERNET TRANSCEIVER mission characters1. For reference, Table 1 shows the mapping of the parallel data to the 8B/10B codes. Loop Back Local loopback provides a capability for performing off-line testing. This is useful for ensuring the integrity of the serial channel before enabling the transmission medium. It also allows for system diagnostics. 1. A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391, May 1982. Table 1. Data Mapping to 8B/10B Alphabetic Representation Data Byte TX[0:9] or RX[0:9] 8B/10B Alphabetic Representation 0 a 1 b 2 c 3 d 4 e 5 i 6 f 7 g 8 h 9 j Figure 2. Functional Block Diagram S2060 TX[0:9] 10 FIFO (4 x 10) 10 Shift Register TXP TXN TBC PLL Clock Multiplier w/ lock detect F0 = F1 x 10 RATEN 2:1 D PLL Clock Recovery w/ lock detect Shift Register RXP RXN EWRAP -LCK_REF EN_CDET Control Logic 10 D Q RX[0:9] COMMA Detect Logic COM_DET RBC0 RBC1 2 March 7, 2001 / Revision H GIGABIT ETHERNET TRANSCEIVER TRANSMITTER DESCRIPTION The S2060 transmitter accepts 10-bit parallel input data and serializes it for transmission over fiber optic or coaxial cable media. The chip is fully compatible with the IEEE 802.3z Gigabit Ethernet standard, and supports the Gigabit Ethernet data rate of 1250.0 Mbps. The S2060 uses a PLL to generate the serial rate transmit clock. The transmitter runs at 10 times the TBC input clock, and operates in either full rate or half rate mode. At the full VCO rate the transmitter runs at 1.25 GHz, while in half rate mode it operates at 625 MHz. S2060 Transmit Byte Clock (TBC) The Transmit Byte Clock input (TBC) must be supplied from a clock source with 100 ppm tolerance to assure that the transmitted data meets the Gigabit Ethernet frequency limits. The internal serial clock is frequency locked to TBC (125.00 MHz). TBC may be 62.5 MHz or 125 MHz, determined by the state of the RATEN input. Operating rates are shown in Table 2. Transmit Latency The average transmit latency is 4 byte times. Parallel-to-Serial Conversion The parallel-to-serial converter takes in 10-bit wide data from the input latch and converts it to a s.


S2060A S2060B S2060C


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)