SN54LS109A

SN54/74LS109A DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and K pins together. LOGIC DIAGRAM DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY SET (SD) 5(11) Q CLEAR (CD) 1(15) CLOCK 4(12) Q 7(9) J 2(14) 6(10) J SUFFIX CERAMIC CASE 620-09 16 1 K 3(13) 16 1 N SUFFIX PLASTIC CASE 648-08 16 MODE SELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load “1” (Set) Hold Toggle Load “0” (Reset) L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H H q q L Q L H H L q q H OUTPUTS 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 5 11 * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the LOW to HIGH clock transition. 2 J SD Q 6 14 J SD Q 10 4 CP 7 CD Q 12 CP 3 K 13 K CD Q 9 1 15 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-181 SN54/74LS109A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage O...