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TDA9144 Dataheets PDF



Part Number TDA9144
Manufacturers NXP
Logo NXP
Description I2C-bus controlled/ alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator
Datasheet TDA9144 DatasheetTDA9144 Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET TDA9144 I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator Preliminary specification File under Integrated Circuits, IC02 1996 Jan 17 Philips Semiconductors Preliminary specification I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator FEATURES • Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM • PALplus helper demodulator • PALplus h.

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INTEGRATED CIRCUITS DATA SHEET TDA9144 I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator Preliminary specification File under Integrated Circuits, IC02 1996 Jan 17 Philips Semiconductors Preliminary specification I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator FEATURES • Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM • PALplus helper demodulator • PALplus helper blanking and EDTV-2 blanking • I2C-bus controlled • I2C-bus addresses hardware selectable • Pin compatible with TDA9141 • Alignment free • Few external components • Designed for use with baseband delay lines • Integrated video filters • Adjustable luminance delay • Noise detector with I2C-bus read-out • Norm/no_norm detector with I2C-bus read-out • CVBS or Y/C input, with automatic detection possibility • CVBS output provided I2C-bus address 8A is used • Vertical divider system • Two-level sandcastle signal • VA synchronization pulse (3-state) • HA synchronization pulse or clamping pulse CLP input/output • Line-locked clock output (6.75 MHz or 6.875 MHz) or stand-alone I2C-bus output port • Stand-alone I2C-bus input/output port • Colour matrix and fast YUV switch • Comb filter enable input/output with subcarrier frequency • Internal bypass mode of external delay line for PALplus and NTSC applications • Low power standby mode with 3-state YUV outputs • Fast blanking detector with I2C-bus read-out • Blanked or unblanked sync on Yout by I2C-bus bit BSY • internal MACROVISION gating for the horizontal PLL enabled by bus bit EMG. ORDERING INFORMATION TYPE NUMBER TDA9144 PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) GENERAL DESCRIPTION TDA9144 The TDA9144 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with helper demodulator for PALplus signals and blanking facilities for PALplus and EDTV-2 signals. The TDA9144 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL/NTSC comb filter. The IC can process both CVBS input signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected, a line-locked clock (LLC) signal is available at the output port pin (6.75 MHz or 6.875 MHz). A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal. Two pins with an input/output port and an output port of the I2C-bus are available. The I2C-bus address of the TDA9144 is hardware programmable. The TDA9144 is pin compatible with the TDA9141 (multistandard decoder/sync processor). VERSION SOT232-1 1996 Jan 17 2 Philips Semiconductors Preliminary specification I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator QUICK REFERENCE DATA SYMBOL VCC ICC VCVBS(p-p) VY(p-p) VC(p-p) VY(out) VY(out) VY(out)(p-p) VU(out)(p-p) VV(out)(p-p) VSC(bl) VSC(clamp) VVA VHA VLLC(p-p) VR,G,B(p-p) Vclamp(I/O) Vsub(p-p) VOPORT PARAMETER positive supply voltage supply current CVBS input voltage (peak-to-peak value) luminance input voltage (peak-to-peak value) chrominance burst input voltage (peak-to-peak value) luminance black-white output voltage luminance PALplus output voltage maximum luminance helper signal output voltage (peak-to-peak value) U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) sandcastle blanking voltage level sandcastle clamping voltage level VA output voltage HA output voltage LLC output voltage amplitude (peak-to-peak value) RGB input voltage (peak-to-peak value) clamping pulse input/output voltage subcarrier output voltage amplitude (peak-to-peak value) port output voltage 0 to 100% saturation standard colour bar standard colour bar black-white top sync-white top sync-white CONDITIONS MIN. 7.2 50 − − − − − − − − 2.2 4.2 4.0 4.0 250 − − 150 4.0 TYP. 8.0 60 1.0 1.0 0.3 1.0 0.8 686 1.33 1.05 2.5 4.5 5.0 5.0 500 0.7 5.0 200 5.0 TDA9144 MAX. 8.8 70 1.43 1.43 0.6 − − − − − 2.8 4.8 5.5 5.5 − 1.0 − 300 5.5 UNIT V mA V V V V V mV V V V V V V mV V V mV V 1996 Jan 17 3 1996 Jan 17 SDA 6 SCL 5 VCC 7 HPLL 24 SC 10 VA 22 ADDR (CVBS) 15 LCA O PORT/LLC 16 SYNC SEPARATOR HORIZONTAL PLL I2C-BUS VERTICAL SYNC SEPARATOR HA TIMING GENERATOR CLP I/O PORT 26 Y/CVBS BLOCK DIAGRAM Philips Semiconductors TRAP handbook, full pagewidth I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with PALplus helper demodulator VA CLP/HA 11 17 R G B F Uout Vout Yout 18 14 13 12 21 20 19 3.


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