Deflection processor for computer controlled TV receivers
INTEGRATED CIRCUITS
DATA SHEET
TDA8433 Deflection processor for computer controlled TV receivers
Product specification ...
Description
INTEGRATED CIRCUITS
DATA SHEET
TDA8433 Deflection processor for computer controlled TV receivers
Product specification File under Integrated Circuits, IC02 August 1991
Philips Semiconductors
Product specification
Deflection processor for computer controlled TV receivers
FEATURES I2C-bus interface Input for vertical sync Sawtooth generator with amplitude independent of frequency Vertical deflection output stage driver East-west raster correction drive output EHT modulation input Changes picture width and height without affecting geometry. QUICK REFERENCE DATA SYMBOL VCC ICC V2 V21 PARAMETER supply voltage (pin 12) supply current (pin 12) vertical sync trigger level vertical feedback (note 1) DC level AC level V24 V11-13 EHT compensation operating range inputs for control register data: not locked to video at 50 Hz status at 60 Hz status V10-13 V14-13 V15 V1 HCENT comparator switching level SDA I2C-bus switching level data input SCL I2C-bus switching level clock input device selection where: Ao = '1' Ao = '0' Note to quick reference data 1. VRin = 0; V-S-corr = 0; Vshift = 20 H; Vampl = 20 H. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS TDA8433 Note 1. SOT101-1; 1996 December 2. August 1991 2 24 PIN POSITION DIL MATERIAL plastic 9.0 0 − − VCC 2.0 − 0.8 VCC − − − − 0.7 − − V17 3.5 3.5 1 − −1.7 1.65 1.7 1.85 1.8 − 2.05 1.95 6 12 − MIN. 10.8 20 3 TYP. 12.0 27 − GENERAL DESCRIPTION The TDA8433 is an I2C-bus controlled deflection processor which, together w...
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