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TDA8315T Dataheets PDF



Part Number TDA8315T
Manufacturers NXP
Logo NXP
Description Integrated NTSC decoder and sync processor
Datasheet TDA8315T DatasheetTDA8315T Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET TDA8315T Integrated NTSC decoder and sync processor Preliminary specification File under Integrated Circuits, IC02 September 1994 Philips Semiconductors Philips Semiconductors Preliminary specification Integrated NTSC decoder and sync processor FEATURES • CVBS or Y/C input • Integrated chrominance trap and bandpass filters (automatically calibrated) • Integrated luminance delay line • Alignment-free NTSC colour decoder • Horizontal PLL with an alignment-free ho.

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INTEGRATED CIRCUITS DATA SHEET TDA8315T Integrated NTSC decoder and sync processor Preliminary specification File under Integrated Circuits, IC02 September 1994 Philips Semiconductors Philips Semiconductors Preliminary specification Integrated NTSC decoder and sync processor FEATURES • CVBS or Y/C input • Integrated chrominance trap and bandpass filters (automatically calibrated) • Integrated luminance delay line • Alignment-free NTSC colour decoder • Horizontal PLL with an alignment-free horizontal oscillator • Vertical count-down circuit • Low dissipation (320 mW) • Small amount of peripheral components compared with competition ICs. QUICK REFERENCE DATA SYMBOL VP IP Input voltages V13(p-p) V15(p-p) Output signals VO(b-w) V21(p-p) V20(p-p) V2 V7 V10 Control voltages Vcontrol control voltages for Saturation and Hue 0 − 5 luminance output voltage (blank-to-white value) −U output voltage (peak-to-peak value) −V output voltage (peak-to-peak value) horizontal sync pulse vertical sync pulse back porch clamping pulse − − − − − − 1.65 1.5 1.5 4 4 4 − − − − − − CVBS/Y input voltage (peak-to-peak value) chrominance input voltage (peak-to-peak value) − − 1 0.3 − − supply current PARAMETER supply voltage (pins 11 and 12) − MIN. 7.2 TYP. 8.0 40 − GENERAL DESCRIPTION TDA8315T The TDA8315T is an alignment-free NTSC decoder/sync processor. The device can be used for normal television applications and for Picture-in-Picture (PIP) applications. The input signal can be either CVBS or Y/C and at the outputs the following signals are available: Luminance signal Colour difference signals (U and V) Horizontal and vertical synchronization pulses Back porch clamping pulse (burst-key pulse). The supply voltage for the IC is 8 V. It is available in a 24-pin SO package. MAX. 8.8 V UNIT mA V V V V V V V V V ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8315T SO24 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm VERSION SOT137-1 September 1994 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... September 1994 DEC DIG DEC BG V P1 V P2 GND1 GND2 9 5 11 12 3 23 COINCIDENCE DETECTOR VERTICAL SYNC SEPARATOR SYNC SEPARATOR CHROMINANCE TRAP CVBS CHROMA CVBS/Y switch 13 15 CVBS/Y SWITCH CHROMINANCE BANDPASS reference 21 NTSC DECODER MATRIX U/V-SIGNALS 18 17 8 SATURATION CONTROL 16 MBE015 BLOCK DIAGRAM Philips Semiconductors Integrated NTSC decoder and sync processor PH1LF 4 PHASE DETECTOR OSCILLATOR PLUS CONTROL PULSE SHAPER 2 HOUT 10 CLAMP VOUT H/V DIVIDER 7 FILTER TUNING LUMINANCE DELAY LINE AMPLIFIER 19 Y DEC FT handbook, full pagewidth 3 U V 20 TDA8315T 14 22 24 SSC HUE PLL XTAL DEM SW SAT Preliminary specification TDA8315T Fig.1 Block diagram. Philips Semiconductors Preliminary specification Integrated NTSC decoder and sync processor PINNING SYMBOL TEST1(1) HOUT GND1 PH1LF DECBG TEST2(1) VOUT DEMSW DECDIG CLAMP VP1 VP2 CVBS/Y DECFT CHROMA SAT SCS HUE Y −V −U PLL GND2 XTAL Note 1. In the application the test pins must be connected to ground. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 test pin 1 horizontal output pulse ground 1 (0 V) phase 1 loop filter bandgap decoupling test pin 2 vertical output pulse demodulation angle switch decoupling digital supply back porch clamping pulse supply voltage 1 (+8 V) supply voltage 2 (+8 V) CVBS/Y input decoupling filter tuning chrominance and switch input saturation control input sub-carrier signal output hue control input Y output −V output −U output PLL colour filter ground 2 (0 V) 3.58 MHz crystal connection handbook, halfpage TDA8315T DESCRIPTION TEST1 HOUT GND1 PH1LF BG DEC TEST2 VOUT DEM SW DEC DIG 1 2 3 4 5 6 TDA8315T 7 8 9 24 XTAL 23 GND2 22 PLL 21 20 19 Y 18 HUE 17 SCS 16 SAT 15 CHROMA 14 DEC FT 13 CVBS/Y MBE016 U V CLAMP 10 V P1 11 V P2 12 Fig.2 Pin configuration. September 1994 4 Philips Semiconductors Preliminary specification Integrated NTSC decoder and sync processor FUNCTIONAL DESCRIPTION CVBS or Y/C input The TDA8315T has a video input which can be switched to CVBS (with internal chrominance bandpass and trap filters) and to Y/C (without chrominance bandpass and trap filters). The switching between CVBS and Y/C is achieved by the DC level of the CHROMA input (pin 15). Integrated video filters The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. The chrominance trap can be switched off by the DC level of the CHROMA input. The luminance delay .


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