TDA8083

INTEGRATED CIRCUITS DATA SHEET TDA8083 Satellite Demodulator and Decoder (SDD3) Product specification File under Integrated Circuits, IC02 1999 Jul 28 Philips Semiconductors Product specification Satellite Demodulator and Decoder (SDD3) FEATURES One chip Digital Video Broadcasting (DVB) (ETS300421) compliant demodulator and concatenated Viterbi and Reed-Solomon decoder with de-interleaver and de-randomizer 3.3 V supply voltage Relevant outputs are 5 V tolerant to ease interface to 5 V environment Few external components for full application On-chip crystal oscillator (4 MHz) and Phase-Locked Loop (PLL) for internal clock generation Power-on reset module QPSK/BPSK demodulator: – Different modulation schemes: Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) – Interpolator and internal anti-aliasing filter to handle variable symbol rates – Tuner Automatic Gain Control (AGC) control – Two on-chip matched 7-bit Analog-to-Digital Converters (ADCs) – Square-root raised-cosine Nyquist – Maximum symbol frequency of 30 Msymbols/s – Can be used at low channel Signal-to-Noise Ratio (S/R) – Internal full digital carrier recovery, clock recovery and AGC loops with programmable loop filters – Two carrier recovery loops enabling optimum phase noise suppression – S/R estimation. Viterbi decoder: – Rate 1⁄2 convolutional code based – Constraint length K = 7 with G1 = 171oct and G2 = 133oct – Supported puncturing code rates: 1⁄2, 2⁄3, 3⁄4, 4⁄5, 5⁄6, 6...