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TDA7503 Dataheets PDF



Part Number TDA7503
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description DUAL DSP PLUS MICRO
Datasheet TDA7503 DatasheetTDA7503 Datasheet (PDF)

® TDA7503 DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS PRODUCT PREVIEW Dual 24-bit 40 MIPS DSP Cores 8 bit Microcontroller 4 receive and 5 transmit stereo channels of Serial Audio Interface Synchronous Serial Interface for communication with external processor FIFO based mailboxes for inter-processor communications External Memory Interface to 128Kb SRAM or 1Mb DRAM CORDIC co-processor Programmable PLL to suite wide range of external crystal oscillation frequencies SPI control interface Powerfu.

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® TDA7503 DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS PRODUCT PREVIEW Dual 24-bit 40 MIPS DSP Cores 8 bit Microcontroller 4 receive and 5 transmit stereo channels of Serial Audio Interface Synchronous Serial Interface for communication with external processor FIFO based mailboxes for inter-processor communications External Memory Interface to 128Kb SRAM or 1Mb DRAM CORDIC co-processor Programmable PLL to suite wide range of external crystal oscillation frequencies SPI control interface Powerful debug interfaces 1280 words Program Memory for DSP1, 768 words Program Memory for DSP0 256 words X and Y Data RAM and Data ROM for each DSP 256 byte Data RAM for Microcontroller 768 byte Auxiliary RAM for Microcontroller BLOCK DIAGRAM TQFP100 DESCRIPTION The device is a high-performance Digital Signal Processing IC particularly suited to Audio applications. The device contains two 24-bit 40 MIPS DSP cores delivering a total of 80 MIPS of DSP processing power. There is also an embedded 8bit Microcontroller to handle all control functions. All data and program memories for both DSP cores are on-chip. A variety of highly programmable and flexible peripheral blocks for both the Microcontroller and the DSPs have been integrated to form a powerful audio processing system on a single chip. Serial Audio Interface Host Interface 0 Host Interface 1 Synchronous Audio Interface XDB0 XAB0 XDB1 XAB1 SRAM/ D RAM Interface XCHG Interface C ordic Ari thmetic U nit M8051 CORE Control Interface AUX-RAM 768 Bytes Y-RAM0 Y-ROM0 PAB0 YDB0 PDB0 YAB0 XDB0 XAB0 YDB1 YAB1 PDB1 PAB1 XDB1 XAB1 Serial Peripheral Interface AUX-RAM 256 Bytes Mi cro Memory Interface Watchdog Timer PLL Clock Oscillator MCLK DCLK Y-RAM1 Y-ROM1 X-RAM0 X-ROM0 X-RAM1 X-ROM1 P-RAM0 P-ROM0 P-RAM1 P-ROM1 DSP0 CORE DSP1 CORE DEBUG Interface July 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/26 TDA7503 ABSOLUTE MAXIMUM RATINGS Symbol VDDC V DDP VI, VIN Top Tstg Core DC Supply voltage Pads DC Supply voltage Digital or analog input voltage Operative temperature range Storage temperature range (plastic) Parameter Value -0.5 to 5 -0.5 to 6.5 -0.5 to (VDDP +0.5) -40 to 85 -55 to 150 Unit V V V °C °C PIN CONNECTION GPIO6(P1.6) GPIO5(P1.5) GPIO4(P1.4) GPIO3(P1.3) GPIO2(P1.2) GPIO1(P1.1) GPIO0(P1.0) VDDE5_MI2 VSSE5_MI2 RAD0(P0.0) RAD1(P0.1) RAD2(P0.2) RAD3(P0.3) RAD4(P0.4) RAD5(P0.5) RAD6(P0.6) RAD7(P0.7) 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 INT0(P3.2) INT1(P3.3) RXD(P3.0) TXD(P3.1) T0(P3.4) WR(P3.6) 85 RD(P3.7) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 xALE 84 83 82 81 80 79 78 77 T1(P3.5) VDDI3_CORE3 VSSI3_CORE3 RESET MISO MOSI SCLK SS/GPIOS VSSE5_CI1 VDDE5_CI1 LRCKR SCLKR SDI3 SDI2 SDI1 SDI0 SDO4 SDO3 SDO2 SDO1 SDO0 VSSI3_CORE2 VDDI3_CORE2 SCLKT LRCKT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1.


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