V62C31864

MOSEL VITELIC V62C31864 2.7 VOLT 8K X 8 STATIC RAM PRELIMINARY Features s High-speed: 35, 70 ns s Ultra low DC operating current of 2mA (Max.) s Low Power Dissipation: – TTL Standby: 1 mA (Max.) – CMOS Standby: 10 mA (Max.) s Fully static operation s All inputs and outputs directly compatible s Three state outputs s Ultra low data retention current (VCC = 2V) s Extended operating voltage: 2.7V–3.6V s Packages – 28-pin TSOP (Standard) – 28-pin 300 mil SOP (450 mil pin-to-pin) Description The V62C31864 is a 65,536-bit static random access memory organized as 8,192 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A0 Row Decoder 512 x 128 Memory Array VCC GND A8 I/O0 Input Data Circuit I/O7 A9 CE2 CE1 OE WE Column I/O Column Decoder A12 Control Circuit 31864 01 Device Usage Chart Operating Temperature Range 0°C to 70 °C –40°C to +85°C Package Outline T F Access Time (ns) 35 70 L Power LL Temperature Mark Blank I V62C31864 Rev. 1.6 August 1998 1 MOSEL VITELIC Pin Descriptions A0–A12 Address Inputs These 13 address inputs select one of the 8,192 x 8 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and...