V62C1161024L

V62C1161024L(L) Ultra Low Power 64K x 16 CMOS SRAM Features Ultra Low-power consumption - Active: 30mA ICC at 70ns - Stand-by: 5 µA (CMOS input/output) 1 µA (CMOS input/output, L version) 70/85/100/120 ns access time Equal access and cycle time Single +1.8V to 2.2V Power Supply Tri-state output Automatic power-down when deselected Multiple center power and ground pins for improved noise immunity Individual byte controls for both Read and Write cycles Available in 44 pin TSOP (II) Package Functional Description The V62C1161024L is a Low Power CMOS Static RAM organized as 65,536 words by 16 bits. Easy memory expansion is provided by an active LOW (CE) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. Writing to these devices is performed by taking Chip Enable (CE) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW. Reading from the device is performed by taking Chip Enable (CE) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) is held HIGH. Logic Block Diagram Pre-Charge Circuit A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 TSOP(II) Row Select Vcc Vss Memory Array 1024 X 1024 I/O1 - I/O8 I/O9 - I/O16 Data Cont Data Cont I/O Circuit Column Select A10 A11 A12 A13 A14 A15 WE OE BHE BLE CE A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 ...