DatasheetsPDF.com

V53C516405A Dataheets PDF



Part Number V53C516405A
Manufacturers Mosel Vitelic Corp
Logo Mosel Vitelic  Corp
Description 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM
Datasheet V53C516405A DatasheetV53C516405A Datasheet (PDF)

MOSEL VITELIC V53C516405A 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C516405A Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60, 70 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hid.

  V53C516405A   V53C516405A


Document
MOSEL VITELIC V53C516405A 4M X 4 EDO PAGE MODE CMOS DYNAMIC RAM V53C516405A Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 4M x 4-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60, 70 ns s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II s Single +5 V ±10% Power Supply s TTL Interface Description The V53C516405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory. The V53C516405A offers Page mode operation with Extended Data Output. The V53C516405A has a symmetric address, 12-bit row and 10-bit column. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 4 bits, within a page, with cycle times as short as 20ns. These features make the V53C516405A ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0°C to 70°C Package Outline K • Access Time (ns) 50 • Power Std. • T • 60 • Temperature Mark Blank V53C516405A Rev. 1.1 March 1998 1 MOSEL VITELIC 24/26 Pin Plastic SOJ /TSOP-II PIN CONFIGURATION Top View VCC I/O1 I/O2 WE RAS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 8 9 10 11 12 13 26 25 24 23 22 21 19 18 17 16 15 14 511740502-02 V53C516405A Pin Names A0–A11 RAS Row, Column Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect VSS I/O4 I/O3 CAS OE A9 A8 A7 A6 A5 A4 VSS CAS WE OE I/O1–I/O4 VCC VSS NC Description SOJ TSOP-II Pkg. K T Pin Count 24/26 24/26 V53C516405A Rev. 1.1 March 1998 2 MOSEL VITELIC Absolute Maximum Ratings* Operating temperature range ..................0 to 70 °C Storage temperature range ............... -55 to 150 °C Input/output voltage ....... -0.5 to min (VCC+0.5, 7) V Power supply voltage ............................-1.0V to 7V Power dissipation .......................................... 1.0 W Data out current (short circuit) ...................... 50 mA *Note: Operation above Absolute Maximum Ratings can adversely affect device reliability. V53C516405A Capacitance* Symbol CIN1 CIN2 COUT TA = 25°C, VCC = 5 V ± 10%, VSS = 0 V, f = 1 MHz Parameter Address Input RAS, CAS, WE, OE Data Input/Output Min. — — — Max. 5 7 7 Unit pF pF pF *Note: Capacitance is sampled and not 100% tested. Block Diagram 4096 x 4 I/O1 I/O2 I/O3 I/O4 Data In Buffer WE CAS 4 Data Out Buffer 4 OE No. 2 Clock Generator 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Column Address Buffers (10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (12) 12 12 Row Address Buffers (12) 12 Row Decoder 4096 Memory Array 4096 x 1024 x 4 1024 x4 4 RAS No. 1 Clock Generator Voltage Down Generator VCC 511640502-03 VCC (internal) V53C516405A Rev. 1.1 March 1998 3 MOSEL VITELIC TA = 0°C to 70°C, VCC = 5 V ± 10%, VSS = 0 V, tT = 2ns, unless otherwise specified. Access Time V53C516405A Min. –10 V53C516405A DC and Operating Characteristics (1-2) Symbol ILI ILO ICC1 Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh VCC Supply Current, EDO Page Mode Operation VCC Supply Current, during CAS-before-RAS Refresh VCC Supply Current, CMOS Standby Typ. Max. 10 Unit µA µA mA Test Conditions VSS ≤ VIN ≤ VCC + 0.5V VSS≤ VOUT ≤ VCC + 0.5V RAS, CAS at VIH tRC = tRC (min.) Notes 1 –10 10 1 50 60 80 70 2 2, 3, 4 ICC2 ICC3 mA RAS, CAS at VIH other inputs ≥ VSS tRC = tRC (min.) 2, 4 50 60 50 60 50 60 80 70 35 30 120 110 1.0 mA ICC4 mA Minimum Cycle 2, 3, 4 ICC5 mA 2, 4 ICC6 mA RAS ≥ VCC – 0.2 V, CAS ≥ VCC – 0.2 V other inputs ≥ VSS 1 VCC VIL VIH VOL VOH Power Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 4.5 –0.5 2.4 5.0 5.5 0.8 V V 1 1 IOL = 4.2 mA IOH = –5 mA 1 1 VCC+0.5 V 0.4 V V 2.4 V53C516405A Rev. 1.1 March 1998 4 MOSEL VITELIC AC Characteristics(5, 6) TA = 0 to 70 ˚C,VCC = 5 V ± 10 %, tT = 2 ns -50 # Symbol Parameter min. max. min. -60 V53C516405A max. Unit Note Common Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period 84 30 50 8 0 8 0 8 12 10 13 40 5 1 – – 50 64 – – 10k 10k –.


V53C516400A V53C516405A V53C517405A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)