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X2804C Dataheets PDF



Part Number X2804C
Manufacturers Xicor
Logo Xicor
Description 5 Volt/ Byte Alterable E2PROM
Datasheet X2804C DatasheetX2804C Datasheet (PDF)

X2804C 4K X2804C 5 Volt, Byte Alterable E2PROM DESCRIPTION 512 x 8 Bit FEATURES • • • • • • • 90ns Access Time Simple Byte and Page Write —Single 5V Supply —No External High Voltages or VPP Control Circuits —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem High Performance Advanced NMOS Technology Fast Write Cycle Times —16 Byte Page Write Operation —Byte or Page Write Cycle: 5ms Typical —Complete Memory Rewrite: 640ms Typical —Effective Byte Writ.

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X2804C 4K X2804C 5 Volt, Byte Alterable E2PROM DESCRIPTION 512 x 8 Bit FEATURES • • • • • • • 90ns Access Time Simple Byte and Page Write —Single 5V Supply —No External High Voltages or VPP Control Circuits —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem High Performance Advanced NMOS Technology Fast Write Cycle Times —16 Byte Page Write Operation —Byte or Page Write Cycle: 5ms Typical —Complete Memory Rewrite: 640ms Typical —Effective Byte Write Cycle Time: 300µs Typical DATA Polling —Allows User to Minimize Write Cycle Time JEDEC Approved Byte-Wide Pinout High Reliability —Endurance: 10,000 Cycles —Data Retention: 100 Years The Xicor X2804C is a 512 x 8 E2PROM, fabricated with an advanced, high performance N-channel floating gate MOS technology. Like all Xicor Programmable nonvolatile memories it is a 5V only device. The X2804C features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs and EPROMs. The X2804C supports a 16-byte page write operation, typically providing a 300µs/byte write cycle, enabling the entire memory to be written in less than 640ms. The X2804C also features DATA Polling, a system software support scheme used to indicate the early completion of a write cycle. Xicor E2PROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years. PIN CONFIGURATION PLASTIC DIP A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 X2804C 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 NC WE OE NC CE I/O7 I/O6 I/O5 I/04 I/O3 6612 FHD F02.1 ©Xicor, Inc. 1993, 1995 Patents Pending 6612-1.3 3/27/96 T2/C1/D1 NS 1 Characteristics subject to change without notice X2804C PIN DESCRIPTIONS Addresses (A0–A8) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. PIN NAMES Symbol A0–A8 I/O0–I/O7 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect 6612 PGM T01 FUNCTIONAL DIAGRAM X BUFFERS LATCHES AND DECODER A0–A8 ADDRESS INPUTS Y BUFFERS LATCHES AND DECODER 4.096-BIT E2PROM ARRAY I/O BUFFERS AND LATCHES I/O0–I/O7 DATA INPUTS/OUTPUTS CE OE WE VCC VSS 6612 FHD F01 CONTROL LOGIC 2 X2804C DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW and WE HIGH. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X2804C supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X2804C allows the entire memory to be typically written in 450ms. Page write allows two to sixteen bytes of data to be consecutively written to the X2804C prior to the commencement of the internal programming cycle. Although the host system may read data from any other device in the system to transfer to the X2804C, the destination page address of the X2804C should be the same on each subsequent strobe of the WE and CE inputs. That is, A4 through A10 must be the same for each transfer of data to the X2804C during a page write cycle. The page write mode can be entered during any write operation. Following the initial byte write cycle, the host can write an additional one to fifteen bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 20µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 20µs, the internal automatic programming cycle will commence. There is no page write window limitation. The page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 20µs. DATA Polling The X2804C features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X2804C, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0.


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