XC7336

® XC7300 CMOS EPLD Family Product Description Features High-performance Erasable Programmable Logic Devices (EPLDs) – 5 / 7.5 ns pin-to-pin speeds on all fast inputs – Up to 167 MHz maximum clock frequency Advanced Dual-Block architecture – Fast Function Blocks – High-Density Function Blocks (XC7354, XC7372, XC73108, XC73144) 100% interconnect matrix High-speed arithmetic carry network – 1 ns ripple-carry delay per bit – 43 to 61 MHz 18-bit accumulators Multiple independent clocks Each input programmable as direct, latched, or registered High-drive 24 mA output I/O operation at 3.3 V or 5 V Meets JEDEC Standard (8-1A) for 3.3 V ± 0.3 V Power management options Multiple security bits for design protection Supported by industry standard design and verification tools 100% PCI compliant Description The XC7300 family employs a unique Dual-Block architecture, which provides high speed operations via Fast Function Blocks and/or high density capability via High Density Function Blocks. Fast Function Blocks (FFBs) provide fast, pin-to-pin speed and logic throughput for critical decoding and ultrafast state machine applications. High-Density Function Blocks (FBs) provide maximum logic density and systemlevel features to implement complex functions with predictable timing for adders and accumulators, wide functions and state machines requiring large numbers of product terms, and other forms of complex logic. In addition, the XC7300 architecture employs the U...