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XC2V1000-6FG456I Dataheets PDF



Part Number XC2V1000-6FG456I
Manufacturers Xilinx
Logo Xilinx
Description Field-Programmable Gate Arrays
Datasheet XC2V1000-6FG456I DatasheetXC2V1000-6FG456I Datasheet (PDF)

0 R Virtex-II 1.5V Field-Programmable Gate Arrays 0 0 DS031-1 (v1.7) October 2, 2001 Advance Product Specification Summary of Virtex®-II Features • • Industry First Platform FPGA Solution IP-Immersion™ Architecture - Densities from 40K to 8M system gates - 420 MHz internal clock speed (Advance Data) - 840+ Mb/s I/O (Advance Data) SelectRAM™ Memory Hierarchy - 3 Mb of True Dual-Port™ RAM in 18-Kbit block SelectRAM resources - Up to 1.5 Mb of distributed SelectRAM resources - High-performance.

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0 R Virtex-II 1.5V Field-Programmable Gate Arrays 0 0 DS031-1 (v1.7) October 2, 2001 Advance Product Specification Summary of Virtex®-II Features • • Industry First Platform FPGA Solution IP-Immersion™ Architecture - Densities from 40K to 8M system gates - 420 MHz internal clock speed (Advance Data) - 840+ Mb/s I/O (Advance Data) SelectRAM™ Memory Hierarchy - 3 Mb of True Dual-Port™ RAM in 18-Kbit block SelectRAM resources - Up to 1.5 Mb of distributed SelectRAM resources - High-performance interfaces to external memory · DDR-SDRAM interface · FCRAM interface · QDR™-SRAM interface · Sigma RAM interface Arithmetic Functions - Dedicated 18-bit x 18-bit multiplier blocks - Fast look-ahead carry logic chains Flexible Logic Resources - Up to 93,184 internal registers / latches with Clock Enable - Up to 93,184 look-up tables (LUTs) or cascadable 16-bit shift registers - Wide multiplexers and wide-input function support - Horizontal cascade chain and Sum-of-Products support - Internal 3-state bussing High-Performance Clock Management Circuitry - Up to 12 DCM (Digital Clock Manager) modules · Precise clock de-skew · Flexible frequency synthesis · High-resolution phase shifting - 16 global clock multiplexer buffers Active Interconnect™ Technology - Fourth generation segmented routing structure - Predictable, fast routing delay, independent of fanout SelectI/O-Ultra™ Technology - Up to 1,108 user I/Os - 19 single-ended standards and six differential standards - Programmable sink current (2 mA to 24 mA) per I/O Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards - PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz compliance, and CardBus compliant - Differential Signaling · 840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers · Bus LVDS I/O · Lightning Data Transport (LDT) I/O with current driver buffers · Low-Voltage Positive Emitter-Coupled Logic (LVPECL) I/O · Built-in DDR Input and Output registers - Proprietary high-performance SelectLink™ Technology · High-bandwidth data path · Double Data Rate (DDR) link · Web-based HDL generation methodology Supported by Xilinx Foundation™ and Alliance™ Series Development Systems - Integrated VHDL and Verilog design flows - Compilation of 10M system gates designs - Internet Team Design (ITD) tool SRAM-Based In-System Configuration - Fast SelectMAP™ configuration - Triple Data Encryption Standard (DES) security option (Bitstream Encryption) - IEEE1532 support - Partial reconfiguration - Unlimited re-programmability - Readback capability 0.15 µm 8-Layer Metal process with 0.12 µm high-speed transistors 1.5 V (VCCINT) core power supply, dedicated 3.3 V VCCAUX auxiliary and VCCO I/O power supplies IEEE 1149.1 compatible boundary-scan logic support Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in three standard fine pitches (0.80mm, 1.00mm, and 1.27mm) 100% factory tested • • • • • • • • • • • • • © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS031-1 (v1.7) October 2, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Module 1 of 4 1 Virtex-II 1.5V Field-Programmable Gate Arrays R Table 1: Virtex-II Field-Programmable Gate Array Family Members CLB (1 CLB = 4 slices = Max 128 bits) System Gates 40K 80K 250K 500K 1M 1.5M 2M 3M 4M 6M 8M Array Row x Col. 8x8 16 x 8 24 x 16 32 x 24 40 x 32 48 x 40 56 x 48 64 x 56 80 x 72 96 x 88 112 x 104 Maximum Distributed RAM Kbits 8 16 48 96 160 240 336 448 720 1,056 1,456 Multiplier Blocks 4 8 24 32 40 48 56 96 120 144 168 SelectRAM Blocks 18-Kbit Blocks 4 8 24 32 40 48 56 96 120 144 168 Max RAM (Kbits) 72 144 432 576 720 864 1,008 1,728 2,160 2,592 3,024 Max I/O Pads(1) 88 120 200 264 432 528 624 720 912 1,104 1,108 Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 Slices 256 512 1,536 3,072 5,120 7,680 10,752 14,336 23,040 33,792 46,592 DCMs 4 4 8 8 8 8 8 12 12 12 12 Notes: 1. See details in Table 2, “Maximum Number of User I/O Pads”. General Description The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and customized modules. The family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications, including PCI, LVDS, and DDR interfaces. The leading-edge 0.15µm / 0.12µm CMOS 8-layer metal process and the Virtex-II architecture are optimized for high speed with low power consumption. Combining a wide variety of flexible features and a large range of densities up to 10 million system gates, the Virtex-II family enhances programmable logic design capabilities and is a powerful alternative to mask.


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