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K9K1208U0A-YIB0 Dataheets PDF



Part Number K9K1208U0A-YIB0
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 64M x 8 Bit NAND Flash Memory
Datasheet K9K1208U0A-YIB0 DatasheetK9K1208U0A-YIB0 Datasheet (PDF)

K9K1208U0A-YCB0, K9K1208U0A-YIB0 Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 FLASH MEMORY History 1. Initial issue - Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection). So, /SE pin is don’ t-cared regardless of external logic input level and is fixed as low internally. Draft Date Dec. 6th 2000 Remark Preliminary 0.1 1. Changed plane address in Copy-Back Program Dec. 28th 2000 - A14, the plane address, of source and destination page address.

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K9K1208U0A-YCB0, K9K1208U0A-YIB0 Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 FLASH MEMORY History 1. Initial issue - Changed /SE(pin # 6, Spare Area Enable) pin to N.C ( No Connection). So, /SE pin is don’ t-cared regardless of external logic input level and is fixed as low internally. Draft Date Dec. 6th 2000 Remark Preliminary 0.1 1. Changed plane address in Copy-Back Program Dec. 28th 2000 - A14, the plane address, of source and destination page address must be the same. => A14 and A25, the plane address, of source and destination page address must be the same. 1. In addition, explain WE function in pin description - The WE must be held high when outputs are activated. Jan. 17th 2001 Final 0.2 Note : For more detailed features and specifications including FAQ, please refer to Samsung’ s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office. 1 K9K1208U0A-YCB0, K9K1208U0A-YIB0 FLASH MEMORY 64M x 8 Bit NAND Flash Memory FEATURES • Voltage Supply : 2.7V~3.6V • Organization - Memory Cell Array : (64M + 2,048K)bit x 8bit - Data Register : (512 + 16)bit x8bit • Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte • 528-Byte Page Read Operation - Random Access : 10µs(Max.) - Serial Page Access : 60ns(Min.) • Fast Write Cycle Time - Program time : 200µ s(Typ.) - Block Erase Time : 2ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years • Command Register Operation • Package : - K9K1208U0A-YCB0/YIB0 : 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch) GENERAL DESCRIPTION The K9K1208U0A are a 64M(67,108,864)x8bit NAND Flash Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528byte page in typically 200µs and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the page can be read out at 60ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9K1208U0A′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K1208U0A-YCB0/YIB0 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. PIN CONFIGURATION PIN DESCRIPTION N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Standard Type 12mm x 20mm 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP R/B VCC VSS N.C Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Ready/Busy output Power Ground No Connection NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave V CC or VSS disconnected. 2 K9K1208U0A-YCB0, K9K1208U0A-YIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM VCC VSS A9 - A25 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders FLASH MEMORY 512M + 16M Bit NAND Flash ARRAY A0 - A7 (512 + 16)Byte x 131072 Page Register & S/A A8 Command Command Register Y-Gating I/O Buffers & Latches VCC VSS I/0 0 I/0 7 CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver CLE ALE WP Figure 2. ARRAY ORGANIZATION 1 Block = 32 Pages = (16K + 512) Byte 128K Pages (=4,096 Blocks) 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 1 Page = 528 Byte 1 Block = 528 Bytes x 32 Pages = (16K + 512) Byte 1 Device = 528Bytes x 32Pages x 4,096 Blocks = 528 Mbits 8 bit 16 Byte 512B Byte Page Register 512 Byte 16 Byte I/O 0 ~ I/O 7 I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle A0 A9 A17 A25 I/O 1 A1 A10 A18 *L I/O 2 A2 A11 A19 *L I/O 3 A3 A12 A20 *L I/O 4 A4 A13 A21 *L I/O 5 A5 A14 A22 *L I/O 6 A6 A15 A23 *L I/O 7 A7 A16 A24 *L Column Address Row Address (Page Address) NOTE : Column Address : Starting Address of the Register. 00h C.


K9K1208U0A-YCB0 K9K1208U0A-YIB0 KS0105


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