ICS97U877

Integrated Circuit Systems, Inc. ICS97U877 1.8V Wide Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR DIMM logic solution with ICSSSTU32864 Product Description/Features: Low skew, low jitter PLL clock driver 1 to 10 differential clock distribution (SSTL_18) Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Auto PD when input signal is at a certain logic state Switching Characteristics: Period jitter: 40ps Half-period jitter: 60ps CYCLE - CYCLE jitter 40ps OUTPUT - OUTPUT skew: 40ps Pin Configuration 1 A B C D E F G H J K 2 3 4 5 6 52-Ball BGA Top View A B C D E F G H J K 1 CLKT1 CLKC1 CLKC2 CLKT2 CLK_INT CLK_INC AGND AVDD CLKT3 CLKC3 2 CLKT0 GND GND VDDQ VDDQ VDDQ VDDQ GND GND CLKC4 3 CLKC0 GND NB VDDQ NB NB VDDQ NB GND CLKT4 4 CLKC5 GND NB VDDQ NB NB VDDQ NB GND CLKT9 5 CLKT5 GND GND OS VDDQ OE VDDQ GND GND CLKC9 6 CLKT6 CLKC6 CLKC7 CLKT7 FB_INT FB_INC FB_OUTC FB_OUTT CLKT8 CLKC8 Block Diagram CLKT0 OE OS AVDD Powerdown Control and Test Logic LD* or OE LD*, OS or OE CLKC0 CLKC1 CLKT2 LD* PLL bypass CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 40 CLK_INT CLK_INC 10K-100k PLL GND FB_INT FB_INC * The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC. CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 FB_OUTT FB_OUTC VDDQ CLKC2 CLKT2 CLK_INT CLK_INC VDDQ AGND AVDD VDDQ GND CLKC1 CLKT1 CLKT0 CLKC0 VD...