SAA7196

INTEGRATED CIRCUITS DATA SHEET SAA7196 Digital video decoder, Scaler and Clock generator circuit (DESCPro) Product specification File under Integrated Circuits, IC22 1996 Nov 04 Philips Semiconductors Product specification Digital video decoder, Scaler and Clock generator circuit (DESCPro) CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.4.1 7.4.2 7.4.3 7.4.3.1 7.4.4 7.4.5 7.4.5.1 7.4.5.2 7.4.5.3 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.10.1 7.4.10.2 7.4.10.3 7.4.10.4 7.4.11 7.4.12 7.5 8 8.1 8.2 8.3 8.4 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Decoder part Chrominance processor Luminance processor Synchronization Expansion port (see Fig.2) Monitor controls BCS (see Fig.2) Brightness and contrast controls; see Tables 1 and 2 Saturation control; see Table 3 RTCO output pin 44 (see Fig.11) RTS1 and RTS0 outputs (pins 34 and 35) Scaler part Decimation filters Vertical processing (VPU_Y) RGB matrix Anti-gamma ROM tables Chrominance signal keyer Scale control and vertical regions Vertical bypass region Vertical scaling region Vertical regions (see Fig.12) Output data representation and levels Output FIFO register and VRAM port VRAM port transfer procedures Data burst transfer mode Transparent data transfer mode Interlaced processing (OF bits, subaddress 20) INCADR timing Monochrome format (see Table 10) VRAM port specifications Field processing Operation cycle Power-on reset PR...