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INTEGRATED CIRCUITS
DATA SHEET
SAA7126H; SAA7127H Digital video encoder
Product specification File under Integrated Circuits, IC22 1999 May 31
Philips Semiconductors
Product specification
Digital video encoder
FEATURES • Monolithic CMOS 3.3 V device, 5 V I2C-bus optionally • Digital PAL/NTSC encoder • System pixel frequency 13.5 MHz • 54 MHz double-speed multiplexed D1 interface capable of splitting data into two separate channels (encoded and baseband) • Four Digital-to-Analog Converters (DACs) for CVBS (CSYNC, VBS), RED (Cr, C), GREEN (Y, VBS) and BLUE (Cb, CVBS) two times oversampled (signals in parenthesis are optionally). RED (Cr), GREEN (Y) and BLUE (Cb) signal outputs with 9-bit resolution, whereas all other signal outputs have 10-bit resolution; CSYNC is an advanced composite sync on the CVBS output for RGB display centring. • Real-time control of subcarrier • Cross-colour reduction filter • Closed captioning encoding and World Standard Teletext (WST) and North-American Broadcast Text System (NABTS) teletext encoding including sequencer and filter • Copy Generation Management System (CGMS) encoding (CGMS described by standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via the I2C-bus • Fast I2C-bus control port (400 kHz) • Line 23 Wide Screen Signalling (WSS) encoding • Video Programming System (VPS) data encoding in line 16 (CCIR line count) • Encoder can be master or slave • Programmable horizontal and vertical input synchronization phase • Programmable horizontal sync output phase • Internal Colour Bar Generator (CBG)
SAA7126H; SAA7127H
• Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; ‘handsfree’ Macrovision pulse support through on-chip timer for pulse amplitude modulation; this applies to SAA7126H only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. • Controlled rise/fall times of output syncs and blanking • On-chip crystal oscillator (3rd-harmonic or fundamental crystal) • Down mode (low output voltage) or power-save mode of DACs • QFP44 package. GENERAL DESCRIPTION The SAA7126H; SAA7127H encodes digital Cb-Y-Cr video data to an NTSC or PAL CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated Cb-Y-Cr signals are available via three additional Digital-to-Analog Converters (DACs). The circuit at a 54 MHz multiplexed digital D1 input port accepts two CCIR compatible Cb-Y-Cr data streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data with overlay and MPEG decoded data without overlay, whereas one data stream is latched at the rising, the other one at the falling clock edge. It includes a sync/clock generator and on-chip DACs.
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7126H SAA7127H QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm VERSION SOT307-2
1999 May 31
2
Philips Semiconductors
Product specification
Digital video encoder
QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD Vi Vo(p-p) RL LElf(i) LElf(d) Tamb BLOCK DIAGRAM PARAMETER analog supply voltage digital supply voltage analog supply current digital supply current input signal voltage levels analog output signal voltages Y, C and CVBS without load (peak-to-peak value) load resistance low frequency integral linearity error low frequency differential linearity error ambient temperature
SAA7126H; SAA7127H
MIN. 3.15 3.0 − − 1.30 75 − − 0
TYP. 3.3 3.3 77 37 1.45 − − − −
MAX. 3.45 3.6 100 46 1.55 300 ±3 ±1 70 V V
UNIT
mA mA V Ω LSB LSB °C
TTL compatible
handbook, full pagewidth
XTALI RESET SDA SCL 40 42 41
RCV1
TTXRQ
LLC1
XTAL 35 34 7
RCV2 8
XCLK 43 37 4
VDDA2 VDDA4 VDDA1 VDDA3 25 28 31 36
VDD(I2C) SA RES
20 21 1 I2C-bus control
I2C-BUS INTERFACE I2C-bus control
SYNC/CLOCK I2C-bus control I2C-bus control Y ENCODER C OUTPUT INTERFACE D 30 CVBS
SAA7126H SAA7127H
Y
clock and timing
MP7 to MP0
9 to 16
MP1 MP2
DATA MANAGER
CbCr
23 TTX 44 I2C-bus control Y n.c. 24, 27 CbCr RGB PROCESSOR 29 A I2C-bus control 26
RED GREEN BLUE
5 VSSD1
18
38
6
17
39
19 RTCI
2 SP
3 AP
22 VSSA1
32
33
VSSD3 VSSD2
VDDD1 VDDD3 VDDD2
VSSA3 VSSA2
MHB498
Fig.1 Block diagram.
1999 May 31
3
Philips Semiconductors
Product specification
Digital video encoder
PINNING SYMBOL TYPE PIN RES SP AP LLC1 VSSD1 VDDD1 RCV1 RCV2 MP7 MP6 MP5 MP4 MP3 MP2 MP1 MP0 VDDD2 VSSD2 RTCI − I I I − − I/O I/O I I I I I I I I − − I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 digital supply voltage 2 digital ground 2 reserved pin; do not connect DESCRIPTION
SAA7126H; SAA7127H
test pin; connected to digital ground for normal operation test pin; connected to digital groun.