SAA6712E

INTEGRATED CIRCUITS DATA SHEET SAA6712E XGA RGB to TFT graphics engine Preliminary specification File under Integrated Circuits, IC02 1999 Aug 25 Philips Semiconductors Preliminary specification XGA RGB to TFT graphics engine CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.7.2 8 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.3.3 FEATURES RGB video input Video processing On screen display Video output Memory interface Miscellaneous GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION Data path System clocks Input interface clock (VCLK) Memory interface clock (MCLKI) I2C-bus interface clock (SCL) System clock (CLK) TFT panel clock (PCLK) RGB input port TFT output port Single pixel mode Double pixel mode Memory port SDRAM memory configuration SGRAM memory configuration I2C-bus interface Scaling algorithm Upscaling Downscaling SYSTEM DESCRIPTION Programming registers Clock management Clock generation and multiplexing Clock divider RGB input interface RGB data sampling Clamp pulse generation Gain correction pulse generation 8.4 8.5 8.5.1 8.5.2 8.5.3 8.6 8.6.1 8.6.2 8.6.3 8.7 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.9 8.10 8.10.1 8.10.2 8.10.3 8.11 8.12 8.12.1 8.12.2 8.12.3 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 SAA6712E Video mode and synchronization signal detection Memory interface Memory interface limitations Initialization of ex...