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SCAN921226SLC Dataheets PDF



Part Number SCAN921226SLC
Manufacturers National Semiconductor
Logo National Semiconductor
Description 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST
Datasheet SCAN921226SLC DatasheetSCAN921226SLC Datasheet (PDF)

SCAN921025/SCAN921226 30-80 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST December 2001 SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST General Description The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226 receives the Bus LVDS serial data stream and transforms it back int.

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SCAN921025/SCAN921226 30-80 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST December 2001 SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST General Description The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. Both devices are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed. The SCAN921025 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-todata and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921025 output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 30 MHz and 80 MHz. Features n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode. n Clock recovery from PLL lock to random data patterns. n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption < 600 mW (typ) @ 80 MHz n Single differential pair eliminates multi-channel skew n 800 Mbps serial Bus LVDS data rate (at 80 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits n Synchronization mode and LOCK indicator n Programmable edge trigger on clock n High impedance on receiver inputs when power is off n Bus LVDS serial output rated for 27Ω load n Small 49-lead BGA package Block Diagrams DS200248-1 © 2001 National Semiconductor Corporation DS200248 www.national.com SCAN921025/SCAN921226 Block Diagrams (Continued) Application DS200248-2 Functional Description The SCAN921025 and SCAN921226 are a 10-bit Serializer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from 30 to 80 MHz. The chipset is also capabl.


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