Document
HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER
November 21, 2000
SC1401
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1401 is a synchronous buck regulator designed to power the latest generation microprocessors in battery operated systems. The SC1401 may be used to provide both the I/O and core voltages utilizing synchronous rectification for the core supply voltage and an LDO N-Channel MOSFET controller for the I/O supply voltage. A 1.25 volt reference allows lower output voltages required by today’s portable microprocessors. The synchronous buck regulator is capable of achieving efficiencies up to 95%. The gate drive circuitry can deliver 2.0A peak currents, allowing the use of N-channel MOSFETs for lower switching and conduction losses. A digital soft start is provided to ensure orderly start up of the power supply without the need for external components. At light load in power save mode, the controller changes mode of operation by missing gate drive cycles, thus reducing gate drive current and improving efficiency. A logic high on PSAVE disables the power saving mode thus reducing noise. The SC1401 is fabricated in a high performance BiCMOS process. This process reduces the power dissipation in low current and shutdown operation modes and improves efficiency. The LDO controller is a high performance positive voltage regulator designed to provide a low noise power source to the microprocessor peripherals by driving a low cost external N-Channel MOSFET.
VIN C1 C2 C3 C4 C5
FEATURES • • • • • • • • •
>90% Efficiency (SMPS) 6.0V to 30V Input range 1.25V to 5.5V Adjustable output (SMPS) PWM and LDO regulator outputs High output gate drive of 2 Amps (SMPS) Power save mode for light load operation 200kHz/300kHz fixed-frequency PWM operation 2mA Typical quiescent current 2µA Typical shutdown current
APPLICATIONS • • •
Notebook and palmtop computers LCD monitors Internet appliances
ORDERING INFORMATION
DEVICE SC1401ISS PACKAGE SSOP-20 TEMP. (TA) -40°C - +85°C
Notes (1) Add suffix “TR” for tape and reel.
TYPICAL APPLICATION CIRCUIT
ENABLE_IO RESET PSAVE U1 SYNC 1 SYNC SC1401ISS PSAVE 20 Q1 SHDN 2 SHDN RESET 19 D1 VO_LINEAR C6 VDD2
3
FB
ENABLEIO
18
R1 C7 C8
4
VDD1
IOS
17 R2 +5V
5 R3 6
GND
GATEIO
16
CSL
VDD2
15 D2
Q2
7
CSH
BST
14 C9 L1 R4 VO_SMPS C12 R5 C13 C14
+5V C10 C11
8
V5V
DH
13
9
DL
PHASE
12 D4
C15
D3
10
PGND
PGND
11
Q3
R6
R7
C16
1 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER
November 21, 2000
SC1401
PIN DESCRIPTION Pin # 1 Pin Name SYNC Pin Function Oscillator control/synchronization input. Connect to V5V for 300kHz. Connect to GND for 200kHz. For external clock synchronization in the 240kHz to 350kHz range. A high-to-low transition causes a new cycle start. Logic Low shuts down the switching regulator. Feedback input for the SMPS. FB selects fixed 1.25V output voltage setting when tied to VOUT. Connect FB to a resistor divider for adjustable output mode. R 8 Refer to page 9. V O (SMPS) = 1.25 • 1 + R9 Supply input from battery (6V to 30V). Low noise analog ground and feedback reference point. Inverting input to current sense amplifier. Also serves as the feedback input in fixed output mode. Non-Inverting input to current sense amplifier. Current limit level is 120mV referenced to CSL. 5 volt external supply used to power the gate drives, internal control and reference of the SC1401. Gate drive output for low side synchronous rectifier MOSFET. Device power ground. Device power ground. Inductor switching node connected to the source of high side MOSFET and drain of low side MOSFET. Gate drive output for high side N-Channel MOSFET. DH is a floating driver output driven from the floating voltage across BST to PHASE. Boost capacitor connection for the high side driver. Supply voltage input for the linear FET controller. Gate drive output for the linear FET controller. Sense input voltage for the adjustable voltage linear FET controller. R 5 Refer to page 9. V O (Linear) = 1.25 • 1 + R6 Logic low shuts down the linear FET controller. Active-Low reset output. A logic low enables power saving mode.
2 3
SHDN FB
4 5 6 7 8 9 10 11 12 13 14 15 16 17
VDD1 GND CSL CSH V5V DL PGND PGND PHASE DH BST VDD2 GATEIO IOS
18 19 20
ENABLEIO RESET PSAVE
Note: All logic level inputs and outputs are open collector TTL compatible.
2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
HIGH PERFORMANCE SYNCHRONOUS BUCK CONTROLLER WITH LDO FOR PORTABLE POWER
November 21, 2000
SC1401
ABSOLUTE MAXIMUM RATINGS
PARAMETER VDD1 to GND PGND to GND V5V, FB, CSH, CSL, IOS to GND SYNC, SHDN, PSAVE, ENABLEIO to GND BST to GND BST to PHASE VDD2 to GND GATEIO to GND Junction operating temperature (TJ) Thermal resistance junction to ambient (θJA) Storage temperature Lead soldering temperature MAXIMUM -0.3 to +.