Document
Si6924EDQ
Vishay Siliconix
N-Channel 2.5-V (G-S) Battery Switch, ESD Protection
PRODUCT SUMMARY
VDS (V)
28
rDS(on) (W)
0.033 @ VGS = 4.5 V 0.038 @ VGS = 3.0 V 0.042 @ VGS = 2.5 V
ID (A)
"4.6 "4.3 "4.1
ESD Protected
2000 V
FEATURES
D D D D Low rDS(on) VGS Max Rating: 14 V Exceeds 2-kV ESD Protection Low Profile TSSOP-8 Package
D rDS(on) Rating at 2.5-V VGS D 28-V VDS Rated D Symetrical Voltage Blocking (Off Voltage)
DESCRIPTION
The Si6924EDQ is a dual n-channel MOSFET with ESD protection and gate over-voltage protection circuitry incorporated into the MOSFET. The device is designed for use in Lithium Ion battery pack circuits. The common-drain contsruction takes advantage of the typical battery pack topology, allowing a further reduction of the device’s on-resistance. The 2-stage input protection circuit is a unique design, consisting of two stages of back-to-back zener diodes separated by a resistor. The first stage diode is designed to absorb most of the ESD energy. The second stage diode is designed to protect the gate from any remaining ESD energy and over-voltages above the gates inherent safe operating range. The series resistor used to limit the current through the second stage diode during over voltage conditions has a maximum value which limits the input current to v 10 mA @ 14 V and the maximum toff to 12 ms. The Si6924EDQ has been optimized as a battery or load switch in Lithium Ion applications with the advantage of both a 2.5-V rDS(on) rating and a safe 14-V gate-to-source maximum rating.
APPLICATION CIRCUITS
D ESD and Overvoltage Protection ESD and Overvoltage Protection R** G
S **R typical value is 1.8 kW by design. Battery Protection Circuit See Typical Characteristics, Gate-Current vs. Gate-Source Voltage, Page 3. *Thermal connection to drain pins is required to achieve specific performance.
FIGURE 1. Typical Use In a Lithium Ion Battery Pack
Document Number: 70814 S-59522—Rev. C, 30-Nov-98
FIGURE 2. Input ESD and Overvoltage Protection Circuit.
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Si6924EDQ
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
*D
*D
TSSOP-8
D S1 S1 G1 1 2 3 4 Top View S1 N-Channel N-Channel S2 D 8 D 7 S2 6 S2 5 G2 1.8 kW G1 G2 1.8 kW
Si6924EDQ
*Thermal connection to drain pins is required to achieve specific performance.
FIGURE 3.
FIGURE 4.
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter
Drain-Source Voltage, Source-Drain Voltage Gate-Source Voltage Continuous Drain-to-Source Current (TJ = 150_C)a, b Pulsed Drain-to-Source Current Pulsed Source Current (Diode Conduction)a, b Maximum Power Dissipationa, b Operating Junction and Storage Temperature Range TA = 25_C TA = 70_C TA = 25_C TA = 70_C
Symbol
VDS VGS ID IDM IS PD TJ, Tstg
Limit
- to + "14 "4.6 "3.7 "20 1.25 1.1 0.72 -55 to 150
Unit
V
A
W _C
THERMAL RESISTANCE RATINGS
Parameter
t v 10 sec Maximum Junction-to-Ambienta Steady-State RthJA 115
Symbol
Typical
Maximum
125
Unit
_C/W
Notes a. Surface Mounted on FR4 Board.