Document
SLS System Logic Semiconductor
SL20T0081
81 COMMON x 132 SEGMENT STN LCD DRIVER / CONTROLLER
SL20T0081
SLS System Logic Semiconductor
SL20T0081
DEVICE SPECIFICATION
OVERVIEW
INTRODUCTION
The SL20T0081 is a single-chip graphic dot-matrix liquid crystal display driver & controller that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the micro-processor. The SL20T0081 contains 81x132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, and the device contains 81 common output circuits and 132 segment output circuits, so that a single chip can drive a 81x132 dot display (capable of displaying 8 columns x 5 rows of a 16 x 16 dot font). Moreover, the capacity of the display can be extended through the use of master/ slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a low-power liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock RC oscillator circuit, the SL20T0081 Series chips can be used to create the lowest power display system with the fewest components for high performance portable systems.
FEATURES
Direct display of RAM data through the display data RAM. RAM capacity : 81x132 = 8580 bits Table 1. Duty and Bias selection Duty 1/81 1/65 1/55 1/49 1/33 RAM bit data : LCD Driver Bias 1/10 or 1/8 1/9 or 1/7 1/8 or 1/6 1/8 or 1/6 1/6 or 1/5 “1” Non-illuminated “0” illuminated (during normal display) Maximum display matrix 81 x 132 65 x 132 55 x 132 49 x 132 33 x 132
High-speed 8-bit MPU interface The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs. Serial interface available (supports write operation only). Abundant command functions Display data Read/Write,display ON/OFF, Normal/Reverse display mode, page address set, display start line set, column address set, status read, display all point ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. Static drive circuit equipped internally for indicators 1 driver, with 4 kinds of flashing mode
SLS System Logic Semiconductor
SL20T0081
Built-in Power Supply Circuit Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of x2 / x3 / x4 / x5, where the step-up voltage reference power supply can be input externally). o High-accuracy voltage adjustment circuit (Thermal gradient -0.05%/ C or external input). LCD driver voltage regulator resistors and voltage followers equipped internally. RC oscillator circuit equipped internally (external clock can also be selected). Operating Voltage Range Supply Voltage (VDD) : 2.4V ~ 3.6V LCD driver Voltage (VLCD) : 4.5V ~ 16.0V Low Power Consumption Operating power Standby power
: 40uA typical (conditions:VDD =3V, x 4 boosting (VCI = VDD ), V0 =11V, Internal power supply ON,display OFF and normal mode is selected ) : 10uA maximum (during power save [standby] mode)
Operating Temperatures o Wide range of operating temperatures : -40 to 85 C CMOS Process Package Type TCP
SLS System Logic Semiconductor
BLOCKDIAGRAM
SL20T0081
SEG131
COM39
COM40
COM79
COM0
VDD
VSS V0 V1 V2 V3 V4 COM Drivers SEG Drivers COM Drivers COMS
CAP1+ CAP1CAP2+ CAP2CAP3+ CAP4+ VOUT VCI VEXT VR IREF IRE HPMB Power Supply Circuit
Display Data Read Circuit FR FRS Row Address Decoder SYNC Timing Generation & Read/Write Circuit CL DISP MS DUTY0 DUTY1 DUTY2 Oscillation Circuit
Display Data Memory 81 x 132 bits
Column Address Decoder
COMS
SEG0
CLS
Command Decoder
Status
MPU Interface
WR (R/W)
D6 (SCK)
RESET
P68/86
D7 (SI)
RD (E)
CE1
CE2
RS
PS
D5
D4
D3
D2
D1
D0
SLS System Logic Semiconductor
PAD CONFIGURATION
PAD Layout
Figure 1. SL20T0081 PAD Layout
282 283 147
SL20T0081
146
Y X
(0,0)
325 104
1
103
Table 2. SL20T0081 PAD Dimensions Item Chip Size Pad No. X 2 to10, 94 to 102, 104 to 146, 148 to 281, 283 to 325 11 to 41, 45-46, 50 to 93 Pad pitch 41-42, 44-45, 46-47, 49-50 42 to 44, 47 to 49 1-2, 102-103, 147-148, 281-282 10-11, 93-94 2 to 10, 94 to 102, 148 to 281 104 to 146, 283 to 325 Bumped PAD size (Bottom) 11 to 41, 45, 46, 50 to 93 42 to 44, 47 to 49 1, 103, 147, 282 Bumped PAD height Figure 2. Align Key Coordination COG Align Key Coordination
30µm 30µm 30µm 30µm 30µm 30µm
Size Y 3000 60 80 110 120 131 90 37 92 57 67 72 18 92 37 92 92 97
Unit
8900
µm
All PAD
ILB Align Key Coordination
60µm
Potting Mark Coordination
72µm
30µm 30µm 30µm
(-4230.0, -1415.0)
30µm
60µm
.