SK100E116

SK10/100E116 HIGH-PER.ORMANCE PRODUCTS Description The SK10/100E116 is a quint differential line receiver designed for use in new, high-performance ECL systems. The receiver design features clamp circuitry to cause a defined output state if both the inverting and non-inverting inputs are left open; in this case the Q output goes low, while the Q* output goes high. This feature makes the device ideal for twisted pair applications. If both inverting and non-inverting inputs are at an equal potential of >–2.9V, the receiver does not go to a defined state, but rather shares current in normal differential amplifier fashion, producing output voltage levels midway between high and low. This may even cause the device to oscillate. The SK10/100E116 provides VBB output for either singleended use or as a DC bias for AC coupling to the device. The VBB output pin should be used only as a DC bias for the E116 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to VCC via a 0.01 µF capacitor. Quint Differential Line Receiver .eatures 500 ps Maximum Propagation Delay Extended VEE Range of –4.2V to –5.5V VBB Output for Single-Ended Reception Internal 75KΩ Input Pull-Down Resistors ESD Protection of >4000V Fully Compatible with MC10E/100E116 Specified Over Industrial Temperature Range: –40oC to +85oC Available in 28-Pin PLCC Package PIN Description Pin D0, D0*–D4, D4* Q0, Q0*-Q4, Q4* VBB VCC0 .unction Differential Input Pairs Diffe...