SM8212B

SM8212B NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Multiframe Pagers - BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing - 1-bit and 2-bit burst error auto-correction function - 25 to 75% duty factor signal coverage - 8 rate error detection condition settings - 76.8 kHz system clock (crystal oscillator) - 76.8 or 38.4 kHz clock output pin - Built-in oscillator capacitor and feedback resistor - 2.0 to 3.5 V operating supply voltage - Molybdenum-gate CMOS process realizes low power dissipation - 16-pin SSOP OVERVIEW The SM8212B is a POCSAG-standard (Post Office Code Standardization Advisory Group) signal processor LSI, which conforms to CCIR recommendation 584 concerning standard international wireless calling codes. The SM8212B supports call messages in either tone, numerical or character outputs at signal speeds of 512, 1200 or 2400 bps. The signal input stage features a built-in filter. Each of the addresses (max. 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenum-gate CMOS structure makes possible the construction of low-voltage operation, low p...