Document
K6F2008V2E Family
Document Title
CMOS SRAM
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No. History
0.0 1.0 1.1 Initial draft Finalize
Draft Date
July 19 , 2001 September 27, 2001
Remark
Preliminary Final Final
Revised May 13, 2003 - Added Lead Free(LF) product for 32-TSOP1-0813.4F(LF) package.
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.1 May 2003
K6F2008V2E Family
256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM FEATURES
• Process Technology: Full CMOS • Organization: 256Kx8 • Power Supply Voltage: 3.0 ~ 3.6V • Low Data Retention Voltage: 1.5V(Min) • Three State Outputs • Package Type: 32-TSOP1-0813.4F, 32-TSOP1-0813.4F(LF)
CMOS SRAM
GENERAL DESCRIPTION
The K6F2008V2E families are fabricated by SAMSUNG′s advanced Full CMOS process technology. The families support industrial temperature ranges for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) Standby (ISB1, Typ) 0.5µA2) Operating (ICC1, Max) 3mA PKG Type
K6F2008V2E-F
Industrial(-40~85°C)
3.0~3.6V
551)/70ns
32-TSOP1-0813.4F 32-TSOP1-0813.4F(LF)
1. The parameter is measured with 30pF test load. 2. Typical values are measured at VCC=3.3V, TA=25°C and not 100% tested.
PIN DESCRIPTION
A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen. Precharge circuit.
Address
32-sTSOP Type1-Forward
Row select
Memory array 1024 rows 256x8 columns
I/O1 I/O8
Data cont
I/O Circuit Column select
Data cont
Name
Function
Name
Function
Address
CS1, CS2 Chip Select Input OE WE Output Enable Write Enable Input
I/O1~I/O8 Data Inputs/Outputs Vcc Vss DNU Power Ground Do Not Use
CS1 CS2 WE OE
A0~A17 Address Inputs
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2
Revision 1.1 May 2003
K6F2008V2E Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F2008V2E-YF55 K6F2008V2E-YF70 K6F2008V2E-LF55 K6F2008V2E-LF70 Function 32-sTSOP1-F, 55ns, 3.3V, LL 32-sTSOP1-F, 70ns, 3.3V, LL 32-sTSOP1-F(LF), 55ns, 3.3V, LL 32-sTSOP1-F(LF), 70ns, 3.3V, LL
CMOS SRAM
FUNCTIONAL DESCRIPTION
CS1 H X
1)
CS2 X
1)
OE X
1) 1)
WE X X
1) 1)
I/O High-Z High-Z High-Z Dout Din
Mode Deselected Deselected Output Disable Read Write
Power Standby Standby Active Active Active
L H H H
X
L L L
H L X1)
H H L
1. X means don′t care (Must be high or low states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.5V -0.2 to 4.6V 1.0 -65 to 150 -40 to 85 Unit V V W °C °C K6F2008V2E-F Remark
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.1 May 2003
K6F2008V2E Family
RECOMMENDED DC OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 3.0 0 2.2 -0.23) Typ. 3.3 0 -
CMOS SRAM
Max 3.6 0 Vcc+0.22) 0.6 Unit V V V V
Note: 1. Industrial Product: TA=-40 to 85°C, unless otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width≤20ns. 3. Undershoot: -2.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(CMOS) VOL VOH ISB1 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL=2.1mA IOH =-1.0mA Other inputs=Vss to Vcc 1) CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or 2) 0V≤CS2≤0.2V CS2 controlled) 2.4 0.5 35 0.4 10 mA V V µA VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc Cycle time=1µs, 100% duty, IIO=0mA, CS1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥VCC-0.2V Test Conditions Min -1 -1 Typ1) Max 1 1 3 Unit µA µA mA
1. Typical value are measured at VCC=3.3V, TA=25°C, and not 100% teste.