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K4S641633H-C Dataheets PDF



Part Number K4S641633H-C
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 1M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA
Datasheet K4S641633H-C DatasheetK4S641633H-C Datasheet (PDF)

K4S641633H - R(B)E/N/G/C/L/F 1M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Functio.

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K4S641633H - R(B)E/N/G/C/L/F 1M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 3.0V & 3.3V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (4K cycle). Commercial Temperature Operation (-25°C ~ 70°C). Extended Temperature Operation (-25°C ~ 85°C). 54Balls FBGA with 0.8mm ball pitch ( -RXXX : Leaded, -BXXX : Lead Free). Mobile-SDRAM GENERAL DESCRIPTION The K4S641633H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4S641633H-R(B)E/N/G/C/L/F75 K4S641633H-R(B)E/N/G/C/L/F1H K4S641633H-R(B)E/N/G/C/L/F1L Max Freq. 133MHz(CL=3) 105MHz(CL=2) 105MHz(CL=3)*1 LVCMOS 54 FBGA Leaded (Lead Free) Interface Package - R(B)E/N/G : Normal / Low / Low Power, Extended Temperature(-25°C ~ 85°C) - R(B)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. February 2004 K4S641633H - R(B)E/N/G/C/L/F FUNCTIONAL BLOCK DIAGRAM Mobile-SDRAM I/O Control LWE Data Input Register Bank Select LDQM 1M x 16 Sense AMP 1M x 16 1M x 16 1M x 16 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register LRAS CLK CKE CLK ADD Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CS RAS CAS WE L(U)DQM February 2004 K4S641633H - R(B)E/N/G/C/L/F Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A B C D1 D E F G H J E E/2 Pin Name CLK D/2 D e A B C D E F G H J 8 7 6 5 4 3 2 1 1 VSS DQ14 DQ12 DQ10 DQ8 UDQM NC A8 VSS Mobile-SDRAM < Top View*2 > 54Ball(6x9) FBGA 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 7 VDDQ VSSQ VDDQ VSSQ VDD CAS BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 WE CS A10 VDD Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm] *2: Top View CS CKE A0 ~ A11 A A1 b BA0 ~ BA1 RAS CAS WE z *1: Bottom View < Top View*2 > #A1 Ball Origin Indicator L(U)DQM DQ0 ~ 15 VDD/VSS VDDQ/VSSQ SEC Week XXXX Symbol A A1 E E1 D D1 e b z Min 0.80 0.27 0.40 - Typ 0.90 0.32 8.00 6.40 8.00 6.40 0.80 0.45 - Max 1.00 0.37 0.50 0.10 K4S641633H February 2004 K4S641633H - R(B)E/N/G/C/L/F ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 Mobile-SDRAM Unit V V °C W mA -55 ~ +150 1.0 50 NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial) Parameter Supply voltage VDDQ Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current VIH VIL VOH VOL ILI 2.7 2.2 -0.3 2.4 -10 3.0 3.0 0 3.6 VDDQ + 0.3 0.5 0.4 10 V V V V V uA 1 2 IOH = -0.1mA IOL = 0.1mA 3 Symbol VDD Min 2.7 Typ 3.0 Max 3.6 Unit V Note NOTES : 1. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outpu.


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