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K4S28323LF-FR60 Dataheets PDF



Part Number K4S28323LF-FR60
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
Datasheet K4S28323LF-FR60 DatasheetK4S28323LF-FR60 Datasheet (PDF)

K4S28323LF - F(H)E/N/S/C/L/R 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • 2.5V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Suppo.

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K4S28323LF - F(H)E/N/S/C/L/R 1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • 2.5V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (4K cycle). Commercial Temperature Operation (-25°C ~ 70°C). Extended Temperature Operation (-25°C ~ 85°C). 90Balls FBGA with 0.8mm ball pitch ( -FXXX : Leaded, -HXXX : Lead Free). Mobile-SDRAM GENERAL DESCRIPTION The K4S28323LF is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4S28323LF-F(H)E/N/S/C/L/R60 K4S28323LF-F(H)E/N/S/C/L/R75 K4S28323LF-F(H)E/N/S/C/L/R1H K4S28323LF-F(H)E/N/S/C/L/R1L Max Freq. 166MHz(CL=3) 133MHz(CL=3) 105MHz(CL=2) 105MHz(CL=3)*1 LVCMOS 90 FBGA Leaded (Lead Free) Interface Package - F(H)E/N/S : Normal/Low/Super Low Power, Extended Temperature(-25°C ~ 85°C) - F(H)C/L/R : Normal/Low/Super Low Power, Commercial Temperature(-25°C ~ 70°C) NOTES : 1. In case of 40MHz Frequency, CL1 can be supported. 2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. February 2004 K4S28323LF - F(H)E/N/S/C/L/R FUNCTIONAL BLOCK DIAGRAM Mobile-SDRAM I/O Control LWE Data Input Register Bank Select LDQM 1M x 32 Sense AMP 1M x 32 1M x 32 1M x 32 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register LRAS CLK CKE CLK ADD Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CS RAS CAS WE DQM February 2004 K4S28323LF - F(H)E/N/S/C/L/R Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A B C D D E F G D1 H J K D/2 L M N P R E E/2 Pin Name CLK CS A A1 Substrate(2Layer) Mobile-SDRAM < Top View*2 > 90Ball(6x15) FBGA 8 7 6 5 4 3 2 1 e A B C D E F G H J K L M N P R 1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 7 VDD VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VDD DQ6 DQ1 VDDQ VDD 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 A11 RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm] CKE A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM0 ~ DQM3 DQ0 ~ 31 b z < Top View*2 > #A1 Ball Origin Indicator SAMSUNG Week VDD/VSS VDDQ/VSSQ K4S28323LF-XXXX Symbol A A1 E E1 D D1 e b z Min 0.30 0.40 - Typ 1.10 0.35 8.00 6.40 13.00 11.20 0.80 0.45 - Max 1.20 0.40 0.50 0.10 February 2004 K4S28323LF - F(H)E/N/S/C/L/R ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 3.6 -1.0 ~ 3.6 Mobile-SDRAM Unit V V °C W mA -55 ~ +150 1.0 50 NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial) Parameter Symbol VDD Supply voltage VDDQ Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current VIH VIL VOH VOL ILI Min 2.3 2.3 1.65 0.8 x VDDQ -0.3 VDDQ -0.2 -10 Typ 2.5 2.5 0 Max 2.7 2.7 2.7 VDDQ + 0.3 0.3 0.2 10 Unit V V V V V V V uA 1 2 3 IOH = -0.1mA IOL = 0.1mA 4 Note NOTES : 1. .


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