K4S281632C-TI

K4S281632C-TI(P) CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) Revision History Revision 0.0 (November 18, 2000) First generation. CMOS SDRAM Revision 0.1 (June 20, 2001) Final Specification. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Industrial Temperature Operation (- 40 to 85 °C) CMOS SDRAM GENERAL DESCRIPTION The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORM...