Document
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
128Mb E-die SDRAM Specification
Revision 1.2 May. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 May. 2003
SDRAM 128Mb E-die (x4, x8, x16)
Revision History
Revision 1.0 (Nov. 2002)
- First release.
CMOS SDRAM
Revision 1.1 (Apr. 2003)
- x4/x8/x16 Merged spec.
Revision 1.2 (May. 2003)
- Delete -TC(L)7C
Rev. 1.2 May. 2003
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4 & 8 ) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x4,x8) & L(U)DQM (x16) for maskin • Auto & self refresh • 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
The K4S280432E / K4S280832E / K4S281632E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. K4S280432E-TC(L)75 K4S280832E-TC(L)75 K4S281632E-TC(L)60/75 Orgainization 32Mb x 4 16Mb x 8 8Mb x 16 Max Freq. 133MHz 133MHz 166MHz Interface LVTTL LVTTL LVTTL Package 54pin TSOP(II) 54pin TSOP(II) 54pin TSOP(II)
Rev. 1.2 May. 2003
SDRAM 128Mb E-die (x4, x8, x16)
Package Physical Dimension
CMOS SDRAM
0~8°C 0.25 TYP 0.010 #54 #28 0.45~0.75 0.018~0.030 0.05 MIN 0.002
11.76±0.20 0.463±0.008
22.62 MAX 0.891 22.22 0.875 0.10 MAX 0.004 ( 0.71 ) 0.028
± 0.10 ± 0.004
0.125+0.075 -0.035 0.005+0.003 -0.001
0.21 0.008
± 0.05 ± 0.002
1.00 0.039
± 0.10 ± 0.004
1.20 MAX 0.047
0.30 -0.05 0.004 0.012 + -0.002
+0.10
0.80 0.0315
54Pin TSOP(II) Package Dimension
Rev. 1.2 May. 2003
( 0.50 ) 0.020
#1
#27
10.16 0.400
SDRAM 128Mb E-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
CMOS SDRAM
I/O Control
LWE LDQM
Data Input Register Bank Select 8M x 4 / 4M x 8 / 2M x 16 Sense AMP 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 8M x 4 / 4M x 8 / 2M x 16 Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS Timing Register
Programming Register LWCBR LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 May. 2003
SDRAM 128Mb E-die (x4, x8, x16)
PIN CONFIGURATION (Top view) x16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD
CMOS SDRAM
x8
x4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
x4
VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
x8
VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
VDD VDD DQ0 N.C VDDQ VDDQ N.C N.C DQ1 DQ0 VSSQ VSSQ N.C N.C DQ2 N.C VDDQ VDDQ N.C N.C DQ3 DQ1 VSSQ VSSQ N.C N.C VDD VDD N.C N.C WE WE CAS CAS RAS RAS CS CS BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD
54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9, CA11 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM.