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S5L9284D Dataheets PDF



Part Number S5L9284D
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description DIGITAL SIGNAL PROCESSOR
Datasheet S5L9284D DatasheetS5L9284D Datasheet (PDF)

DIGITAL SIGNAL PROCESSOR S5L9284D INTRODUCTION The S5L9284D is a CMOS integrated circuit designed for the digital audio signal processor. It is a monolithic IC with built-in 16K SRAM and DPLL. It is similar to S5L9283 IC but has advanced error correction ability. 80−QFP−1420C FEATURES • • • • • • • • • • • • • EFM data demodulation Built-in frame sync detection, protection and insertion circuit C1: 2 error correction; C2: 4 erasure correction Interpolation Subcode data serial output CLV serv.

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DIGITAL SIGNAL PROCESSOR S5L9284D INTRODUCTION The S5L9284D is a CMOS integrated circuit designed for the digital audio signal processor. It is a monolithic IC with built-in 16K SRAM and DPLL. It is similar to S5L9283 IC but has advanced error correction ability. 80−QFP−1420C FEATURES • • • • • • • • • • • • • EFM data demodulation Built-in frame sync detection, protection and insertion circuit C1: 2 error correction; C2: 4 erasure correction Interpolation Subcode data serial output CLV servo controller Tracking counter MICOM interface Built-in 16K SRAM Digital audio output (TX) Built-in digital PLL and analog PLL Double speed function Single power supply: +5V ORDERING INFORMATION Device S5L9284D01-Q0R0 Package 80-QFP-1420C Operating Temperature −20°C to +75°C 1 S5L9284D DIGITAL SIGNAL PROCESSOR BLOCK DIAGRAM KCBS TDBS 26 SUBCODE SYNC DETECTOR 1S0S 32 33 30 SQDT SUBCODE OUTPUT SUBCODE REGISTER 29 SQCK EFMI 66 APDO2 80 APDO1 67 VCOI 78 CNTVOL DPFIN DPFOUT DPDO 5 3 DPLL 4 2 FRAME SYNC DETECTOR PROTECTOR INSERTER EFM PHASE DETECTOR 23 BITS SHIFT REGISTER EFM DEMODULATOR ECC SMEF 72 16K SRAM SMON 73 SMDP 75 SMSD 76 LOCK 70 XIN XOUT 8 9 X-TAL TIMING GENERATOR CLV SERVO ADDRESS GENERATOR SUB ATAD TIB-8 MLT 36 MDAT 37 MCK 38 DSPEED 79 /ISTAT 68 TRCNT 69 MODE SELECTOR CPU INTERFACE TRACK COUNTER INTERPOLATOR DIGITAL OUTPUT 61 62 63 64 65 22 7 15 12 21 11 20 O P2C 1HCRL 2HCRL 1TDAS 2TDAS 1LES 2LES 3LES 4LES XTAD 1TSET 0TSET 2 DIGITAL SIGNAL PROCESSOR S5L9284D PIN CONFIGURATION DSPEED APDO2 APDO1 DVDD2 TRCNT /ISTAT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AVDD1 DPDO DPFIN DPFOUT CNTVOL AVSS1 DATX XIN XOUT WDCH1 LRCH1 SADT1 DVSS1 BCK1 C2PO TIM2 /BCK1 /BCK2 BCK2 LRCH2 SADT2 TEST0 WDCH2 EMPH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TEST1 SMON VCOO SMDP SMSD SMEF PBFR VCOI LOCK EFMI 64 63 62 61 60 59 58 57 56 SEL4 SEL3 SEL2 SLE1 /CS /WE C16M C4M /JIT ULKFS FSDW DVSS2 /PBCK FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 DB0 DB1 DB2 DB3 DB4 DB5 KS9284 S5L9284D 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S0S1 DB7 MLT RESET MDAT SQDT SBDT MUTE SQOK SQCK SBCK LKFS DVDD1 SQEN MCK DB6 3 S5L9284D DIGITAL SIGNAL PROCESSOR PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol AVDD1 DPDO DPFIN DPFOUT CNTVOL AVSS1 DATX XIN XOUT WDCH1 LRCH1 SADT1 DVSS1 BCK1 C2PO TIM2 /BCK1 /BCK2 BCK2 LRCH2 SADT2 TEST0 WDCH2 EMPH LKFS S0S1 RESET SQEN SQCK SQDT SQOK I/O − O I O I − O I O O O O − O O O O O O O O I O O O O I I I/O O O Analog supply voltage 1 Charge pump output for master PLL Filter input for master PLL Filter output for master PLL VCO control voltage for master PLL Analog ground 1 Digital audio output X-tal oscillator input (16.9344MHz / 33.8688MHz) X-tal oscillator output Word clock of 48 bits/slot Channel clock of 48 bits/slot Serial audio data output with 48 bits/slot Digital ground 1 Serial audio data bit clock for 48 bits/slot C2 pointer for serial audio data Normal or double speed control output pin Inverted clock of BCK1 Inverted clock of BCK2 Serial audio data bit clock for 64 bits/slot Channel clock for 64 bits/slot Serial audio data output with 64 bits/slot Test input pin ( “L”: normal, “H”: test) Word clock of 64 bit/slot Emphasis/Non-emphasis output (“H”: Emphasis) The lock status output of frame sync Output of subcode sync signal (S0 + S1) System reset at Low SQCK control input (“L”: internal clock, “H”: external clock) Subcode-Q data bit clock Subcode-Q data serial output The CRC check result signal output of subcode-Q Description 4 DIGITAL SIGNAL PROCESSOR S5L9284D PIN DESCRIPTION (Continued) Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Symbol SBCK SBDT DVDD1 MUTE MLT MDAT MCK DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 /PBCK DVSS2 FSDW ULKFS /JIT C4M C16M /WE / CS SEL1 SEL2 I/O I O − I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O − I/O I/O I/O I/O I/O I/O I/O I I Subcode data bit clock Subcode serial data output Digital supply voltage 1 Mute control input (“H ”: Mute ON) Latch signal input from micom Serial data input from micom Serial data transferring clock input from micom Data port 7 for external SRAM (MSB) Data port 6 for external SRAM Data port 5 for external SRAM Data port 4 for external SRAM Data port 3 for external SRAM Data port 2 for external SRAM Data port 1 for external SRAM Data port 0 for external SRAM (LSB) Monitoring output for C1 error correction (RA0) Monitoring output for C1 error correction (RA1) Monitoring output for C2 error correction (RA2) Monitoring output for C2 error correction (RA3) C2 decoder flag ( “H”: when the processing C2 code is in impossible correction status /RA4) VCOI/2 clock (4.3218/8.6436 MHz), when locked in with EFMI (RA5) Digital ground 2 Unprotected frame sync (RA6) Frame sync protectio.


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