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S3C7032 Dataheets PDF



Part Number S3C7032
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description The S3C7031/7032 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core.
Datasheet S3C7032 DatasheetS3C7032 Datasheet (PDF)

S3C7031/7032 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVER VIEW The S3C7031/7032 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core. With comparator inputs, high-current LED direct-drive pins, serial I/O interface, and a versatile 8-bit timer/counter, the S3C7031/7032 offers an excellent design solution for a wide range of applications such as mouse controllers, subsystem controllers, and toys. Up to 15 pins of the 20-pin DIP or 20-pin SO.

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S3C7031/7032 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVER VIEW The S3C7031/7032 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core. With comparator inputs, high-current LED direct-drive pins, serial I/O interface, and a versatile 8-bit timer/counter, the S3C7031/7032 offers an excellent design solution for a wide range of applications such as mouse controllers, subsystem controllers, and toys. Up to 15 pins of the 20-pin DIP or 20-pin SOP package can be dedicated to I/O. Pull-up resistors are assignable to all of the pins by software. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C7031/7032's advanced CMOS technology provides for very low power consumption and a wide operating voltage range. DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for KS57-series microcontrollers that is powerful, reliable, and portable. In addition to its easy to use window-oriented program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications. The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard object files that also contain program control data for SMDS compatibility. 1-1 PRODUCT OVERVIEW S3C7031/7032 FEATURES Memory — 1024 × 8-bit program memory (S3C7031) (ROM) — 2048 × 8-bit program memory (S3C7032) (ROM) — 128 × 4-bit data memory (S3C7031) (RAM) — 256 × 4-bit data memory (S3C7032) (RAM) I/O Pins — Up to 15 pins for 20-DIP and 20-SOP package Comparator Inputs — 4-channel mode Internal reference: 4-bit resolution — 3-channel mode External reference 8-Bit Basic Timer — Programmable interval timer 8-Bit Timer/Counter — Programmable interval timer — External event counter function — Timer clock output to TIO pin Watch Timer — Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz — Four frequency outputs to BUZ pin Bit Sequential Carrier — 16-bit serial data transfer in arbitrary format 8-Bit Serial I/O Interface — 8-bit transmit/receive mode — 8-bit receive-only mode — LSB-first or MSB-first transmission selectable — Internal or external clock source Interrupts — One external interrupt vector — Three internal interrupt vectors — Two quasi-interrupts Memory-Mapped I/O Structure Two Power-Down Modes — Idle mode: Only the CPU clock stops — Stop mode: Main system clock stops On-Chip Crystal, Ceramic, Or RC Oscillator — Crystal/ceramic: 4.19 MHz (typical) — RC: 1 MHz (typical) — CPU clock divider circuit (by 4, 8, or 64) Frequency Outputs — Eight frequency outputs to the CLO pin Instruction Execution Times — 0.95, 1.91, 15.3 µs at 4.19 MHz (5 V), 4 µs at 1 MHz (2.7 V) Operating Temperature: — – 40°C to 85°C Operating Voltage Range: — 2.7 V to 6.0 V Package Type: — 20-DIP, 20-SOP 1-2 S3C7031/7032 PRODUCT OVERVIEW BLOCK DIAGRAM RESET Basic Timer Interrupt Control Block Watch Timer Internal Interrupts P2.0 - P2.3 P3.0/SCK P3.1/SO P3.2/SI P3.3/BUZ I/O Port 2 XIN XOUT I/O Port 0 P0.0/CLO P0.1/TIO P0.2/INT1 Clock Stack Pointer Program Counter 8-Bit Timer/ Counter Instruction Decoder I/O Port 3 Arithmetic and Logic Unit Serial I/O Port Program Status Word Comparator Flags I/O Port 1 P0.0/KS0/CIN0 P0.1/KS1/CIN1 P0.2/KS2/CIN2 P0.3/KS3/CIN3 Data Memory (2) Program Memory (1) NOTES: 1. Program Memory is 1-KByte (S3C7031) and 2-KByte (S3C7032). 2. Data Memory is 128 x 4bit (S3C7031) and 256 x 4bit (S3C7032). Figure 1-1. S3C7031/7032 Block Diagram 1-3 PRODUCT OVERVIEW S3C7031/7032 PIN ASSIGNMENTS P0.0/CLO P0.1/TIO P0.2/INT1 P0.0/KS0/CIN0 P0.1/KS1/CIN1 P0.2/KS2/CIN2 P0.3/KS3/CIN3 XOUT XIN VSS 1 2 3 4 5 6 7 8 9 10 KS57C7031/ KS57C7032 (Top view) 20 19 18 17 16 15 14 13 12 11 VDD P3.3/BUZ P3.2/SI P3.1/SO P3.0/SCK P2.3 P2.2 P2.1 P2.0 RESET NOTE: Pin assignments are identical for the 20-pin DIP and SOP package. Figure 1-2. S3C7031/7032 Pin Assignment Diagram (20-pin DIP/SOP Package) PIN DESCRIPTIONS Table 1-1. S3C7031/7032 Pin Descriptions Pin Name P0.0 P0.1 P0.2 Pin Type I/O Description 3-bit I/O port. 1-bit or 3-bit read/write and test is possible. Pull-up resistors are individually assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. Same as port 0 except that port 1 is a 4-bit I/O port. Number 1 2 3 Share Pin CLO TIO INT1 P1.0 P1.1 P1.2 P1.3 I/O 4 5 6 7 KS0/CIN0 KS1/CIN1 KS2/CIN2 KS3/CIN3 1-4 S3C7031/7032 PRODUCT OVERVIEW Table 1-1. S3C7031/7032 Pin Descriptions (Continued) Pin Name P2.0-P2.3 P3.0 P3.1 P3.2 P3.3 Pin Type I/O Description 4-bit I/O port. 1-bit, 4-bit or 8-bit read/write and test is possible. Pins are individually configurable as input or output. Pull-up resistors are indivi.


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