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IDT70T659S Dataheets PDF



Part Number IDT70T659S
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
Datasheet IDT70T659S DatasheetIDT70T659S Datasheet (PDF)

Features ◆ ◆ HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ ◆ ◆ PRELIMINARY IDT70T651/9S ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 8/10/12/15ns (max.) – Industrial: 10/12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T651/9 easily expands data bus width to 72 bi.

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Features ◆ ◆ HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE ◆ ◆ ◆ PRELIMINARY IDT70T651/9S ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 8/10/12/15ns (max.) – Industrial: 10/12ns (max.) RapidWrite Mode simplifies high-speed consecutive write cycles Dual chip enables allow for depth expansion without external logic IDT70T651/9 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Busy and Interrupt Flags On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Sleep Mode Inputs on both ports Supports JTAG features compliant to IEEE 1149.1 Single 2.5V (±100mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad Flatpack and 208-ball fine pitch Ball Grid Array. Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram BE3L BE2L BE1L BE0L BE 3R BE2R BE 1R BE0R R/W L CE0L CE1L BB EE 01 LL BB EE 23 LL BBBB EEEE 3210 R RRR R/WR CE0R CE1R OEL Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R Dout18-26_L Dout18-26_R Dout27-35_L Dout27-35_R OER 256/128K x 36 MEMORY ARRAY I/O0L- I/O 35L Di n_L Di n_R I/O 0R - I/O 35R A 17L(1) A0L Address Decoder ADDR_L ADDR_R Address Decoder A17R(1) A0R CE0L CE1L OEL R/WL BUSYL (2,3) SEM L INTL(3) ZZL (4) ARBITRATION INTERRUPT SEMAPHORE LOGIC OE R R/WR CE0R CE1R TDI TD O JTAG TC K TMS TRST M/S BUSYR(2,3) SEMR INT R(3) ZZR (4) LOGIC NOTES: 1. Address A17x is a NC for IDT70T659. 2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/ S=VIH). 3. BUSY and INT are non-tri-state totem-pole outputs (push-pull). 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INT x, M/S and the sleep mode pins themselves (ZZx) are not affected during sleep mode. ZZ CONTROL 4869 drw 01 NOVEMBER 2003 DSC-5632/3 1 ©2003 Integrated Device Technology, Inc. IDT70T651/9S High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down Description feature controlled by the chip enables (either CE0 or CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. The IDT70T651/9 has a RapidWrite Mode which allows the designer to perform back-to-back write operations without pulsing the R/W input each cycle. This is especially significant at the 8 and 10ns cycle times of the IDT70T651/9, easing design considerations at these high performance levels. The 70T651/9 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controlled by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V. 2 IDT70T651/9S High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Preliminary Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3) 70T651/9BC BC-256(5,6) 256-Pin BGA Top View A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 03/18/03 A1 NC B1 TDI B2 NC B3 A17L(4) A14L B4 B5 A11L B6 A 8L B7 BE2L B8 CE1L B9 OEL B10 INTL B11 A5L B12 A2L B13 A0L B14 NC B15 NC B16 I/O18L C1 NC C2 TDO C3 NC C4 A15L C5 A12L C6 A 9L C7 BE3L C8 CE0L R/WL C9 C10 NC C11 A4L C12 A1L C13 NC C14 I/O17L C15 NC C16 I/O18R I/O19L VSS D1 D2 D3 A16L D4 A13L D5 A10L D6 A7L D7 BE1L BE0L SEML BUSYL A6L D8 D9 D10 D11 D12 A3L D13 OPTL I/O17R I/O16L D14 D15 D16 I/O20R I/O19R I/O20L E1 E2 E3 VDD E4 VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 I/O21R I/O21L I/O22L VDDQL VDD F1 F2 F3 F4 F5 VDD F6 VSS F7 VSS F8 V SS F9 VSS F10 VDD F11 VDD VDDQR I/O13L I/O14L I/O14R F12 F13 F14 F15 F16 I/O23L I/O22R I/O23R VDDQL VDD G1 G2 G3 G4 G5 NC G6 VSS G7 VSS G8 V SS G9 VSS G10 VSS G11 VDD VDDQR I/O12R I/O13R I/O12L G12 G13 G14 G15 G16 I/O24R I/O24L I/O25L VDDQR VSS H.


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