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IDT74FCT16601ET Dataheets PDF



Part Number IDT74FCT16601ET
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Datasheet IDT74FCT16601ET DatasheetIDT74FCT16601ET Datasheet (PDF)

Integrated Device Technology, Inc. FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS IDT74FCT16601AT/CT/ET IDT74FCT162601AT/CT/ET PRODUCT PREVIEW bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg• Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in either direction in a transparent, – High-speed, low-power CMOS replacement fo.

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Integrated Device Technology, Inc. FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS IDT74FCT16601AT/CT/ET IDT74FCT162601AT/CT/ET PRODUCT PREVIEW bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg• Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in either direction in a transparent, – High-speed, low-power CMOS replacement for latched or clocked mode. Each direction has an independent ABT functions latch enable, an independent clock with a clock enable, and an – Typical tSK(o) (Output Skew) < 250ps independent output enable. The package is organized with a – Low input and output leakage ≤1µ A (max.) flow-through signal pin organization to ease board layout. All – ESD > 2000V per MIL-STD-883, Method 3015; inputs are designed with hysteresis for improved noise mar> 200V using machine model (C = 200pF, R = 0) gin. – Packages include 25 mil pitch SSOP, 19.6 mil pitch This transceiver is ideally suited for high speed memory TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack interfaces which utilize high speed synchronous writes, by – Extended commercial range of -40°C to +85°C clocking the data into a high speed register. Reads can then – VCC = 5V ±10% be performed in a transparent or latched mode utilizing the • Features for FCT16601AT/CT/ET: same transceiver. – High drive outputs (-32mA IOH, 64mA IOL) The FCT16601AT/CT/ET are ideally suited for driving – Power off disable outputs permit “live insertion” high-capacitance loads and low-impedance backplanes. The – Typical VOLP (Output Ground Bounce) < 1.0V at output buffers are designed with power off disable capability VCC = 5V, TA = 25°C to allow "live insertion" of boards when used as backplane • Features for FCT162601AT/CT/ET: drivers. – Balanced Output Drivers: ±24mA The FCT162601AT/CT/ET have balanced output drive – Reduced system switching noise with current limiting resistors. This offers low ground bounce, – Typical VOLP (Output Ground Bounce) < 0.6V at minimal undershoot, and controlled output fall times–reducing VCC = 5V,TA = 25°C the need for external series terminating resistors. The FCT162601AT/CT/ET are plug-in replacements for the DESCRIPTION: FCT16601AT/CT/ET and ABT16601 for on-board bus interThe FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications. FEATURES: P R E V IE W FUNCTIONAL BLOCK DIAGRAM OEAB CLKENAB CLKAB LEAB LEBA CLKBA CLKENBA OEBA 1 56 55 2 28 30 P 29 27 3 R O D U C T A1 CE 1D C1 CLK CE 1D C1 CLK 54 B1 3247 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. TO 17 OTHER CHANNELS COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. AUGUST 1996 5.9 DSC-3247/- 1 IDT74FCT16601AT/CT/ET, 162601AT/CT/ET FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATIONS OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 56 55 54 53 52 51 50 49 48 47 46 45 44 CLKENAB CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max. VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0 GND –0.5 to VTERM(3) Terminal Voltage with Respect to GND VCC +0.5 TSTG Storage Temperature –65 to +150 I OUT DC Output Current –60 to +120 Unit V V °C mA 3247 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. 14 SO56-1 43 SO56-2 15 SO56-3 42 16 17 18 19 20 21 22 23 24 25 26 27 28 41 40 39 38 37 36 35 34 33 32 31 30 29 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance CI/O I/O Capacitance NOTE: 1. This parameter is measured at characterization but not tested. P R E V IE W Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0 pF 3247 lnk 04 CLKBA SSOP/ TSSOP/TVSOP TOP VIEW PIN DESCRIPTION Pin Names OEAB OEBA LEAB LEBA CLKAB CLKBA Ax Bx A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs A to B Clock Enable Input B to A Clock Enable Input 3247 tbl 01 P Description R O CLKENBA D U C T FUNCTION TABLE(1,4) CLKENAB X X X H L OEAB H L L L L L L L Inputs LEAB X H H L L L L L CLKAB X X X X ↑ ↑ .


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