Document
3.3V CMOS 20-BIT BUFFERS
Integrated Device Technology, Inc.
IDT74FCT163827A/B/C
FEATURES:
• 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP • Extended commercial range of -40°C to +85°C • VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range • CMOS power levels (0.4µW typ. static) • Rail-to-Rail output swing for increased noise margin • Low Ground Bounce (0.3V typ.) • Inputs (except I/O) can be driven by 3.3V or 5V components
DESCRIPTION:
The FCT163827A/B/C 20-bit buffers are built using advanced dual metal CMOS technology. These 20-bit bus drivers provide high-performance bus interface buffering for wide data/address paths or busses carrying parity. Two pairs of NAND-ed output enable controls offer maximum control flexibility and are organized to operate the device as two 10bit buffers or one 20-bit buffer. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163827A/B/C have series current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The inputs of the FCT163827A/B/C can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V supply system.
FUNCTIONAL BLOCK DIAGRAM
1OE1 1OE2
2OE 1 2OE2
1A1
1Y1
2A1
2Y1
TO 9 OTHER CHANNELS
3083 drw 01
TO 9 OTHER CHANNELS
3083 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
AUGUST 1996
8.9
DSC-3083/3
1
IDT74FCT163827A/B/C FAST CMOS 20-BIT BUFFERS
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
PIN DESCRIPTION
Pin Names xOEx Description Output Enable Inputs (Active LOW) Data Inputs 3-State Outputs
3083 tbl 01
1OE1 1Y1 1Y2
1 2 3 4 5 6 7 8 9 10 11 12 13
56 55 54 53 52 51 50 49 48 47 46 45 44
1OE2 1A1 1A2
xAx xYx
GND
1Y3 1Y4
GND
1A3 1A4
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) VTERM(4) TSTG I OUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max. –0.5 to +4.6 –0.5 to +7.0 –0.5 to VCC + 0.5 –65 to +150 –60 to +60 Unit V V V
VCC
1Y5 1Y6 1Y7
VCC
1A5 1A6 1A7
°C
mA
GND
1Y8 1Y9 1Y10 2Y1 2Y2 2Y3
GND
1A8 1A9 1A10 2A1 2A2 2A3
14 SO56-1 43 SO56-2 15 SO56-3 42 16 17 18 19 20 21 22 23 24 25 26 27 28 41 40 39 38 37 36 35 34 33 32 31 30 29
3083 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Output and I/O terminals.
GND
2Y4 2Y5 2Y6
GND
2A4 2A5 2A6
FUNCTION TABLE(1)
xOE1 L L H X Inputs xOE2 L L X H xAx L H X X Outputs xYx L H Z Z
3083 tbl 02
VCC
2Y7 2Y8
VCC
2A7 2A8
GND
2Y9 2Y10 2OE1
GND
2A9 2A10 2OE2
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance
SSOP/ TSSOP/TVSOP TOP VIEW
3083 drw 03
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. Unit 6.0 pF 8.0
pF
NOTE: 1. This parameter is measured at characterization but not tested.
3083 lnk 04
8.9
2
IDT74FCT163827A/B/C FAST CMOS 20-BIT BUFFERS
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 2.7V to 3.6V
Symbol VIH VIL II H II L I OZH I OZL VIK I ODH I ODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VCC = Max. VCC = Max. VI = 5.5V VI = VCC VI = GND VI = GND VO = V CC VO = GND VCC = Min., IIN = –18mA VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) VCC = 3.3V, V IN = VIH or VIL, VO = 1.5V(3) VCC = Min. VIN = VIH or V IL VCC = 3.0V VIN = VIH or V IL VCC = Min. VIN = VIH or V IL I OH = –0.1mA I OH = –3mA I OH = –8mA I OL = 0.1mA I OL = 16mA I OL = 24mA VCC = 3.0V I OL = 24mA VIN = VIH or V IL VCC = Max., VO = GND(3)
—
Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level
Min. 2.0 2.0 –0.5 — — — — — — — –36 50 VCC– 0.2 2.4 2.4 (5).