Document
3.3 VOLT CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
IDT72V201, IDT72V211 IDT72V221, IDT72V231 IDT72V241, IDT72V251
FEATURES:
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256 x 9-bit organization IDT72V201 512 x 9-bit organization IDT72V211 1,024 x 9-bit organization IDT72V221 2,048 x 9-bit organization IDT72V231 4,096 x 9-bit organization IDT72V241 8,192 x 9-bit organization IDT72V251 10 ns read/write cycle time 5V input tolerant Read and Write clocks can be independent Dual-Ported zero fall-through time architecture Empty and Full Flags signal FIFO status Programmable Almost-Empty and Almost-Full flags can be set to any depth Programmable Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output Enable puts output data bus in high-impedance state Advanced submicron CMOS technology Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin plastic Thin Quad FlatPack (TQFP) Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™ are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. The architecture, functional operation and pin assignments are identical to those of the IDT72201/72211/72221/72231/ 72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and 3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit memory array, respectively. These FIFOs are applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and two Write Enable pins (WEN1, WEN2). Data is written into the Synchronous FIFO on every rising clock edge when the Write Enable pins are asserted. The output port is controlled by another clock pin (RCLK) and two Read Enable pins ( REN1, REN2). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF). Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are provided for improved system control. The programmable flags default to Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag offset loading is controlled by a simple state machine and is initiated by asserting the Load pin (LD). These FIFOs are fabricated using IDT's high-speed submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK WEN1 WEN2 INPUT REGISTER OFFSET REGISTER EF PAE PAF FF D0 - D8 LD
WRITE CONTROL LOGIC RAM ARRAY 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9
FLAG LOGIC
WRITE POINTER
READ POINTER
READ CONTROL LOGIC
OUTPUT REGISTER RESET LOGIC RCLK REN1 REN2 RS OE Q0 - Q8
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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©2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2002
DSC-4092/2
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
RS D2 D3 D4 D5 D6 D7 D8
D2
D3
D4
D5
D6
D7
INDEX
INDEX
32 31 30 29 28 27 26 25 D1 D0 PAF PAE GND REN1 RCLK REN2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5
4 D1 D0 PAF PAE GND REN1 RCLK REN2 OE 5 6 7 8 9 10 11 12 13
3
2 1
32 31 30 29 28 27 26 25 24 23 22 21 RS WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5
14 15 16 17 18 19 20
EF
FF
Q0
Q1
Q2
Q3
OE EF
Q0
Q1
Q2
Q3
FF
Q4
Q4
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D8
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TQFP (PR32-1, order code: PF) TOP VIEW
PLCC (J32-1, order code: J) TOP VIEW
PIN DESCRIPTIONS
Symbol D0-D8
RS
WCLK
WEN1
WEN2/LD
Q0-Q8 RCLK
REN1 REN2 OE EF PAE PAF FF
VCC GND
I/O Description I Data inputs for a 9-bit bus. I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF go HIGH, and PAE and EF go LOW. A Reset is required before an initial Write after power-up. Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted. Write Enable 1 I If the FIFO is configured to have programmable flags, WEN1 is the only Write Enable pin. When WEN1 is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. Write Enable 2/ I The FIFO is configured at Reset to have e.