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IDT72125 Dataheets PDF



Part Number IDT72125
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description CMOS PARALLEL-TO-SERIAL FIFO
Datasheet IDT72125 DatasheetIDT72125 Datasheet (PDF)

CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16 IDT72125 FEATURES: • 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-Full, and Almost- Empty/Almost-Full • Dual-Port zero fall-through architecture • Available in 28-pin 300 mil plastic DIP and 28-pin SOIC • Green par.

  IDT72125   IDT72125


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CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16 IDT72125 FEATURES: • 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-Full, and Almost- Empty/Almost-Full • Dual-Port zero fall-through architecture • Available in 28-pin 300 mil plastic DIP and 28-pin SOIC • Green parts available, see ordering information DESCRIPTION: The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial FIFO. This FIFO features a 16-bit parallel input port and a serial output port with 1,024 word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/ tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT’s unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, Full,Half-FullandAlmost-Empty/Almost-Full. TheFullandEmptyflagsprevent anyFIFOdataoverfloworunderflowconditions. TheHalf-FullFlagisavailable in both single and expansion mode configurations. The Almost-Empty/AlmostFull Flag is available only in a single device mode. The IDT72125 is fabricated using submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM RS W D0-15 16 RESET LOGIC WRITE POINTER RAM ARRAY 1,024 x 16 READ POINTER RSIX RSOX FL/DIR EXPANSION LOGIC SERIAL OUTPUT LOGIC SOCP SO FLAG LOGIC FF EF HF AEF 2665 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1 © 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2016 DSC-2665/1 IDT72125 PARALLEL-TO-SERIAL CMOS FIFO 1,024 x 16 COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION W D0 D1 D2 D3 D4 D5 D6 D7 EF FF HF RSIX GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 Vcc 27 D15 26 D14 25 D13 24 D12 23 D11 22 D10 21 D9 20 D8 19 RS 18 SO 17 SOCP 16 RSOX/AEF 15 FL/DIR 2665 drw 02 PLASTIC THIN DIP (P28, order code: TP) SOIC (SO28, order code: SO) TOP VIEW PIN DESCRIPTIONS Symbol Name I/O D0–D15 Inputs I RS Reset I W Write I SOCP FL/DIR SerialOutputClock I FirstLoad/Direction I RSIX Read Serial In I Expansion SO Serial Output O FF Full Flag O EF Empty Flag O HF RSOX/AEF VCC GND Half-Full Flag Read Serial Out Expansion Almost-Empty, Almost-Full Flag Power Supply Ground O O Data inputs for 16-bit wide data. Description When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset. A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. This is a dual purpose input used in the width and depth expansion configurations. The First Load (FL) function is programmed only during Reset (RS) and a LOW on FL indicates the first device to be loaded with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first. In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX is connected to RSOX (expansion out) of the previous device. Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the Direction pin programming. During Expansion the SO pins are tied together. When FF goes LOW, the device is full and further WRITE operations are inhibited. When FF is HIGH, the device is not full. When EF goes LOW, the device is empty and further READ operations are inhibited. When EF is HIGH, the device is not empty. When HF is LOW, the device is more than half-full. When HF is HIGH, the device is empty to half-full. This is a dual purpose output. In the single device configuration (RSIX HIGH), this is an AEF output pin. When AEF is LOW, the device is empty-to-(1/8 full -1) or (7/8 full +1)-to-full. When AEF is HIGH, the .


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