74AC280

® 74AC280 9 BIT PARITY GENERATOR s s s s s odd/even parity outputs (ΣODD and ΣEVEN). The nine data inputs control the output conditions. s When the number of high level input is odd, ΣODD output is kept high and ΣEVEN output low. s Conservely, when the output is even, ΣEVEN s output is kept high and ΣODD low. The IC generates either odd or even parity DESCRIPTION making it flexible application. The AC280 is an advanced high-speed CMOS 9 The word-length capability is easily expanded by www.DataSheet4U.com BIT PARITY GENERATOR fabricated with cascading. sub-micron silicon gate and double-layer metal All inputs and outputs are equipped with 2 wiring C MOS technology. It is ideal for low protection circuits against static discharge, giving power applications mantaining high speed them 2KV ESD immunity and transient excess operation similar to equivalent Bipolar Schottky voltage. TTL. It is composed of nine data inputs (A to I) and s HIGH SPEED: tPD = 4 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 280 IMPROVED LATCH-UP IMMUNITY B M (Plastic Package) (Micro Package) ORDER CODES : 74AC280B 74AC280M PIN CONNECTION AND IEC LOGIC SYMBOLS December 1998 1/8 74AC280 INPUT ...