74AC245

74AC245 OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (NON INVERTED) s s s s s s s s s HIGH SPEED: tPD = 4.5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 244 IMPROVED LATCH-UP IMMUNITY DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE 74AC245B 74AC245M T&R 74AC245MTR 74AC245TTR DIR input. The enable input G can be used to disable the device so that the buses are effectively DESCRIPTION isolated.. The 74AC245 is an advanced high-speed CMOS www.DataSheet4U.com All floating bus terminals during HIGH-Z state OCTAL BUS TRANSCEIVER (3-STATE) must be held HIGH or LOW fabricated with sub-micron silicon gate and All inputs and outputs are equipped with double-layer metal wiring C2MOS tecnology. protection circuits against static discharge, giving This IC is intended for two-way asynchronous them 2KV ESD immunity and transient excess communication between data buses and the voltage. direction of data transmission is determined by PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/9 74AC245 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 19 10 20 SYMBOL DIR A1 to A8 B1 to B8 NAME AND FUNCTION Directional Co...