74ABT273A

INTEGRATED CIRCUITS 74ABT273A Octal D-type flip-flop Product specification IC23 Data Handbook 1995 Sep 06 Philips Semiconductors Philips Semiconductors Product specification Octal D-type flip-flop 74ABT273A FEATURES Eight edge-triggered D-type flip-flops Buffered common clock Buffered asynchronous Master Reset Power-up reset See 74ABT377 for clock enable version See 74ABT373 for transparent latch version See 74ABT374 for 3-State version ESD protection exceeds 2000 V per Mil Std 833 Method 3015 and 200 V per machine model. DESCRIPTION The 74ABT273A has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced Low independent of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are common elements. QUICK REFERENCE DATA SYMBOL tPLH tPHL CIN ICCH PARAMETER Propagation delay CP to Qn Input capacitance Total supply current CONDITIONS Tamb = 25°C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs High; VCC =5.5V TYPICAL 3.0 3.4 3.5 150 UNIT ns pF µA ORDERING INFORMATION PACKAGES 20-Pin Plastic DIP 20-Pin plastic SO ...