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74F112 Dataheets PDF



Part Number 74F112
Manufacturers NXP
Logo NXP
Description Dual J-K negative edge-triggered flip-flop
Datasheet 74F112 Datasheet74F112 Datasheet (PDF)

INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb 09 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74F112 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. T.

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INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb 09 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74F112 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. TYPE 74F112 TYPICAL PROPAGATION DELAY 100MHz PIN CONFIGURATION CP0 K0 J0 SD0 Q0 Q0 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD0 RD1 CP1 K1 J1 SD1 Q1 SF00103 TYPICAL SUPPLY CURRENT (TOTAL) 15mA ORDERING INFORMATION ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F112N N74F112D INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C I74F112N I74F112D PKG DWG # SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS J0, J1 K0, K1 SD0, SD1 RD0, RD1 CP0, CP1 Q0, Q0; Q1, Q1 J inputs K inputs Set inputs (active Low) Reset inputs (active Low) Clock Pulse input (active falling edge) Data outputs DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/5.0 1.0/5.0 1.0/4.0 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 20µA/0.6mA 20µA/3.0mA 20µA/3.0mA 20µA/2.4mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. February 9, 1990 2 853–0338 98775 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74F112 LOGIC SYMBOL 3 11 2 12 IEC/IEEE SYMBOL 3 1 1J C1 1K R S 6 5 1 4 15 13 10 14 J0 CP0 SD0 RD0 CP1 J1 K0 K1 2 15 4 11 SD1 RD1 Q0 Q0 Q1 Q1 13 12 14 10 VCC = Pin 16 GND = Pin 8 5 6 9 7 2J C2 2K R S 7 9 SF00104 SF00105 LOGIC DIAGRAM 5, 9 Qn 6, 7 Qn 4, 10 SDn 2, 12 Kn 15, 14 RDn 3, 11 Jn VCC = Pin 16 GND = Pin 8 1, 13 CPn SF00106 FUNCTION TABLE INPUTS SD L H L H H H H H RD H L L H H H H H CP X X X ↓ ↓ ↓ ↓ H J X X X h l h l X K X X X h h l l X OUTPUTS Q H L H* q L H q Q Q L H H* q H L q Q Asynchronous Set Asynchronous Reset Undetermined * Toggle Load “0” (Reset) Load “1” (Set) Hold “no change” Hold “no change” OPERATING MODE H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously. February 9, 1990 3 Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74F112 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range free air temperature range Operating free-air Storage temperature range Industrial range PARAMETER RATING –0.5 to +7.0 –0.5 to +7.0 –30 to +5 –0.5 to VCC 40 0 to +70 –40 to +85 –65 to +150 UNIT V V mA V mA °C °C °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free-air free air temperature range Industrial range 0 –40 PARAMETER MIN 4.5 2.0 0.8 –18 –1 20 +70 +85 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA °C °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX VIH = MIN, IOH = MAX Low level output voltage Low-level Input clamp voltage Input current at maximum input voltage High-level input current Jn, Kn IIL IOS Low-level input current current3 CPn SDn, RDn Short-circuit output VCC = MAX –60 VCC = MAX, VI = 0.5V VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V ±10%VCC ±5%VCC ±10%VCC ±5%VCC LIMITS MIN 2.5 2.7 3.4 0.35 0.35 –0.73 0.50 0.50 –1.2 100 20 –0.6 –2.4 –3.0 –150 V µA µA mA mA mA mA V TYP2 MAX UN.


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